head 1.3; access; symbols; locks; strict; comment @# @; 1.3 date 2001.10.19.04.38.33; author rudi; state Exp; branches; next 1.2; 1.2 date 2001.09.07.15.34.38; author rudi; state Exp; branches; next 1.1; 1.1 date 2001.07.29.08.57.02; author rudi; state Exp; branches; next ; desc @@ 1.3 log @ - Changed library to WC @ text @################################################################################# # # Library Specification # # Author: Rudolf Usselmann # rudi@@asics.ws # # Revision: # 3/7/01 RU Initial Sript # # ################################################################################# # ============================================== # Setup Libraries set search_path [list $search_path . \ /tools/dc_libraries/virtual_silicon/UMCL18U250D2_2.2/design_compiler/ \ $hdl_src_dir] set snps [getenv "SYNOPSYS"] set synthetic_library "" append synthetic_library $snps "/libraries/syn/dw01.sldb " append synthetic_library $snps "/libraries/syn/dw02.sldb " append synthetic_library $snps "/libraries/syn/dw03.sldb " append synthetic_library $snps "/libraries/syn/dw04.sldb " append synthetic_library $snps "/libraries/syn/dw05.sldb " append synthetic_library $snps "/libraries/syn/dw06.sldb " append synthetic_library $snps "/libraries/syn/dw07.sldb " set target_library { umcl18u250t2_wc.db } set link_library "" append link_library $target_library " " $synthetic_library set symbol_library { umcl18u250t2.sdb } @ 1.2 log @ Changed reset to active high. @ text @d32 1 a32 1 set target_library { umcl18u250t2_typ.db } @ 1.1 log @ 1) Changed Directory Structure 2) Added restart signal (REST) @ text @d18 1 a18 1 /tools/dc_libraries/umc/umc_0.18/UMCL18U250D2_2.1/design_compiler/ \ @