head 1.2; access; symbols; locks; strict; comment @# @; 1.2 date 2001.08.07.08.00.44; author rudi; state Exp; branches; next 1.1; 1.1 date 2001.07.29.08.57.02; author rudi; state Exp; branches; next ; desc @@ 1.2 log @ Split up priority encoder modules to separate files @ text @################################################################################# # # Design Specification # # Author: Rudolf Usselmann # rudi@@asics.ws # # Revision: # 3/7/01 RU Initial Sript # # ################################################################################# # ============================================== # Setup Design Parameters set design_files {wb_dma_inc30r wb_dma_ch_arb wb_dma_pri_enc_sub wb_dma_ch_pri_enc wb_dma_ch_sel wb_dma_ch_rf wb_dma_rf wb_dma_wb_mast wb_dma_wb_slv wb_dma_wb_if wb_dma_de wb_dma_top } set design_name wb_dma_top set active_design wb_dma_top # Next Statement defines all clocks and resets in the design set special_net {rst clk} set hdl_src_dir ../../rtl/verilog/ @ 1.1 log @ 1) Changed Directory Structure 2) Added restart signal (REST) @ text @d17 1 a17 1 set design_files {inc30_r wb_dma_ch_arb wb_dma_ch_pri_enc wb_dma_ch_sel wb_dma_ch_rf wb_dma_rf wb_dma_wb_mast wb_dma_wb_slv wb_dma_wb_if wb_dma_de wb_dma_top } @