| TOC |
|
A synthesizable 8-bit microprocessor which is instruction-set compatable with the Z80, targetted at embedded and system-on-a-chip designs.
1.
Background
2.
Core Area and Technology Mapping
3.
TV80 Peripherals
3.1
Simple GMII Interface
3.1.1
Register Interface
4.
Verification Environment
4.1
Memory Map
4.2
Control Registers
4.2.1
Simulation control (0x80)
4.2.2
Message output (0x81)
4.2.3
Timeout control (0x82)
4.2.4
Max timeout (0x84, 0x83)
4.2.5
Interrupt countdown (0x90)
4.2.6
Checksum value (0x91)
4.2.7
Checksum accumulate (0x92)
4.2.8
Increment on read (0x93)
4.3
Tool Chain
4.4
Tests
4.4.1
tvs80 test
5.
References
§
Author's Address
| TOC |
The tv80 core was created as a Verilog port of the VHDL T80 coreWallner, D., VHDL T80 Core, .[1], for use as a maintenence processor inside an ASIC. The tv80 has been modified since then for better synthesis timing/area results, and to incorporate several bug-fixes.
The T80, and the tv80 derived from it, attempt to maintain the original cycle timings of the Z80, but have radically different internal designs and timings. With its target being ASIC and embedded applications, the tv80 does not attempt to maintain the original pinout of the Z80.
| TOC |
This section tracks synthesis results in various technologies. LSI 10K technology is used as a baseline because the library ships with Design Compiler.
Component Clock Speed Area Technology (units)
================ =========== ======== =====================
tv80 33 Mhz 10733 lsi_10k (gates)
simple_gmii 33 Mhz 1247 lsi_10k (gates)
| TOC |
The TV80 design includes a number (one, at this point) of peripherals. These peripherals are hardware-synthesizable, but may not be fully tested or functional.
This block presents a GMII interface on one side and a TV80 processor interface on the other. The processor-side controls are all mapped into I/O-space. The block can only process a single packet in each direction at one time. This is only really a limitation on the RX side, where any incoming packets will be dropped until the processor removes the first packet from the RX buffer.
The GMII interface is signalling only, and does not support 10/100 operation, half duplex mode, flow control, or any other aspects of 802.3.
This block consumes 3 bits of I/O address space. The register addresses below are relative to the configurable base address of the block, which must be aligned to an 8-byte boundary. Registers 0x6 and 0x7 are reserved.
Bit 0 of the status register indicates that a packet is available in the RX buffer. This bit will be cleared when the last byte of data is read out of the RX buffer.
Bit 1 is set when the packet in the TX buffer has finished transmitting. This bit will be cleared when the first byte of data of the next packet is written into the TX buffer.
This register is read-only.
Bit 0 controls sending packets. When a 1 is written to this bit, the data in the TX buffer will be sent as a single packet.
This register is write-only.
This register contains the low 8 bits of the length of the packet currently residing in the RX buffer.
This register is read-only.
This register contains the high 8 bits of the length of the packet currently residing in the RX buffer.
This register is read-only.
This register contains the next byte of data in the RX packet buffer.
This register is read-only.
Writing to this register puts data in the TX packet buffer. This register does not perform bounds checking; it is the program's responsibility not to write more data than the size of the TX buffer.
This register is write-only.
| TOC |
Environment memory space is divided into a 32k ROM region and a 32k RAM region, as follows:
0000-7FFF: ROM 8000-FFFF: RAM
Environment I/O space is allocated as follows:
00-0F: Unused 10-1F: Test devices 20-7F: Unused 80-9F: Environment control A0-FF: Unused
Write characters to this port one at a time. When the newline ('\n', ASCII 0x0A) character is written, the environment will print out the collected string.
Bit[0] enables the timeout counter, Bit[1] resets the counter to 0. Timeout counter defaults to enabled at simulation start.
Holds 16-bit timeout value (amount of time in clocks before timeout error occurs).
When set, starts a countdown (in clocks) until assertion of the INT_N signal.
This register holds the checksum value of all data written to the accumulate register. The checksum is a simple twos-complement checksum, so it can be compared with a CPU-generated checksum.
This register is readable and writeable. Writing the register sets the current checksum value.
This write-only register adds the written value to the value contained in the Checksum Value register.
This register increments every time it is read, so reading it repeatedly generates an incrementing sequence. It can be reset by writing it to a new starting value.
The minimum toolchain required to simulate the tv80 is the CVerVanvick, A., GPL Cver Simulator, .[3] Verilog simulator, and the SDCC, Small Device C Compiler, .[2] compiler/assembler/linker. In addition, to run the tvs80tvs80 test instruction test suite, the DOSBox, DOSBox, .[4] DOS emulator is required.
Most of the tests in the tv80 environment are written in C, and should be compiled with the sdcc, Small Device C Compiler, .[2] compiler.
The tvs80 test is different than the rest of the tests, and is written in its own flavor of assembly language. This test provides a fairly comprehensive Z80 instruction test.
The assembler for this test only runs under DOS. To assemble under Unix/Linux, the "dosbox" DOS emulator, DOSBox, .[4] is required. A script to run the assembler under dosbox, as well as the tvs80.asm source, is checked in under the "tests/tvs80" directory.
| TOC |
| [1] | Wallner, D., "VHDL T80 Core". |
| [2] | "Small Device C Compiler". |
| [3] | Vanvick, A., "GPL Cver Simulator". |
| [4] | "DOSBox". |
| TOC |
| Guy Hutchison | |
| OpenCores.org | |
| EMail: | ghutchis@@opencores.org |