head 1.3; access; symbols rel_1_1:1.3 rel_1_0:1.3 rel_0_6_1_beta:1.1 rel_0_6__beta:1.1 rel_0_6_beta:1.1 rel_0_5_beta:1.1 rel_0_4_beta:1.1 rel_0_3_beta:1.1 rel_0_2_beta:1.1 rel_0_1_beta:1.1; locks; strict; comment @# @; 1.3 date 2006.06.22.00.21.28; author arniml; state Exp; branches; next 1.2; commitid 3d594499e2854567; 1.2 date 2006.06.21.01.04.05; author arniml; state Exp; branches; next 1.1; commitid 584f44989b034567; 1.1 date 2004.03.24.21.42.10; author arniml; state Exp; branches; next ; desc @@ 1.3 log @added external ROM @ text @------------------------------------------------------------------------------- -- -- The testbench for t8048. -- -- $Id: tb_t8048-c.vhd,v 1.2 2006/06/21 01:04:05 arniml Exp $ -- -- Copyright (c) 2004, Arnim Laeuger (arniml@@opencores.org) -- -- All rights reserved -- ------------------------------------------------------------------------------- configuration tb_t8048_behav_c0 of tb_t8048 is for behav for ext_ram_b : generic_ram_ena use configuration work.generic_ram_ena_rtl_c0; end for; for ext_rom_b : lpm_rom use configuration work.lpm_rom_c0; end for; for t8048_b : t8048 use configuration work.t8048_struct_c0; end for; end for; end tb_t8048_behav_c0; ------------------------------------------------------------------------------- -- File History: -- -- $Log: tb_t8048-c.vhd,v $ -- Revision 1.2 2006/06/21 01:04:05 arniml -- replaced syn_ram and syn_rom with generic_ram_ena and t48_rom/t49_rom/t3x_rom -- -- Revision 1.1 2004/03/24 21:42:10 arniml -- initial check-in -- ------------------------------------------------------------------------------- @ 1.2 log @replaced syn_ram and syn_rom with generic_ram_ena and t48_rom/t49_rom/t3x_rom @ text @d5 1 a5 1 -- $Id: tb_t8048-c.vhd,v 1.1 2004/03/24 21:42:10 arniml Exp $ d21 4 d38 3 @ 1.1 log @initial check-in @ text @d5 1 a5 1 -- $Id: tb_t8048-c.vhd,v 1.2 2004/03/20 20:03:56 arnim Exp $ d17 2 a18 2 for ext_ram_b : syn_ram use configuration work.syn_ram_lpm_c0; d33 4 a36 1 -- $Log$ @