head     1.1;
branch   1.1.1;
access   ;
symbols  vlsi:1.1.1.1 marta:1.1.1;
locks    ; strict;
comment  @# @;


1.1
date     2002.02.09.14.32.44;  author marta;  state Exp;
branches 1.1.1.1;
next     ;

1.1.1.1
date     2002.02.09.14.32.44;  author marta;  state Exp;
branches ;
next     ;


desc
@@



1.1
log
@Initial revision
@
text
@-- VHDL structural description generated from `zero1`
--		date : Mon Jul 30 17:44:30 2001


-- Entity Declaration

ENTITY zero1 IS
  PORT (
  a : out BIT;	-- a
  vdd : in BIT;	-- vdd
  vss : in BIT	-- vss
  );
END zero1;

-- Architecture Declaration

ARCHITECTURE VST OF zero1 IS
  COMPONENT zero_x0
    port (
    nq : out BIT;	-- nq
    vdd : in BIT;	-- vdd
    vss : in BIT	-- vss
    );
  END COMPONENT;


BEGIN

  a : zero_x0
    PORT MAP (
    vss => vss,
    vdd => vdd,
    nq => a);

end VST;
@


1.1.1.1
log
@no message
@
text
@@