head 1.1; branch 1.1.1; access ; symbols vlsi:1.1.1.1 marta:1.1.1; locks ; strict; comment @# @; 1.1 date 2002.02.09.14.33.55; author marta; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2002.02.09.14.33.55; author marta; state Exp; branches ; next ; desc @@ 1.1 log @Initial revision @ text @-- VHDL structural description generated from `leftshifter` -- date : Mon Sep 10 08:44:01 2001 -- Entity Declaration ENTITY leftshifter IS PORT ( p : in BIT_VECTOR (16 DOWNTO 0); -- p q : in BIT_VECTOR (15 DOWNTO 0); -- q r0 : out BIT_VECTOR (31 DOWNTO 0); -- r0 r1 : out BIT_VECTOR (31 DOWNTO 0); -- r1 r2 : out BIT_VECTOR (31 DOWNTO 0); -- r2 r3 : out BIT_VECTOR (31 DOWNTO 0); -- r3 r4 : out BIT_VECTOR (31 DOWNTO 0); -- r4 r5 : out BIT_VECTOR (31 DOWNTO 0); -- r5 r6 : out BIT_VECTOR (31 DOWNTO 0); -- r6 r7 : out BIT_VECTOR (31 DOWNTO 0); -- r7 r8 : out BIT_VECTOR (31 DOWNTO 0); -- r8 r9 : out BIT_VECTOR (31 DOWNTO 0); -- r9 r10 : out BIT_VECTOR (31 DOWNTO 0); -- r10 r11 : out BIT_VECTOR (31 DOWNTO 0); -- r11 r12 : out BIT_VECTOR (31 DOWNTO 0); -- r12 r13 : out BIT_VECTOR (31 DOWNTO 0); -- r13 r14 : out BIT_VECTOR (31 DOWNTO 0); -- r14 r15 : out BIT_VECTOR (31 DOWNTO 0); -- r15 r16 : out BIT_VECTOR (31 DOWNTO 0); -- r16 vdd : in BIT; -- vdd vss : in BIT -- vss ); END leftshifter; -- Architecture Declaration ARCHITECTURE VST OF leftshifter IS COMPONENT a2_x2 port ( i0 : in BIT; -- i0 i1 : in BIT; -- i1 q : out BIT; -- q vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; COMPONENT zero_x0 port ( nq : out BIT; -- nq vdd : in BIT; -- vdd vss : in BIT -- vss ); END COMPONENT; BEGIN r16_0 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(0)); r16_1 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(1)); r16_2 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(2)); r16_3 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(3)); r16_4 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(4)); r16_5 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(5)); r16_6 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(6)); r16_7 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(7)); r16_8 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(8)); r16_9 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(9)); r16_10 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(10)); r16_11 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(11)); r16_12 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(12)); r16_13 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(13)); r16_14 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(14)); r16_15 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(15)); r16_16 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(16)); r16_17 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(17)); r16_18 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(18)); r16_19 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(19)); r16_20 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(20)); r16_21 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(21)); r16_22 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(22)); r16_23 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(23)); r16_24 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(24)); r16_25 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(25)); r16_26 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(26)); r16_27 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(27)); r16_28 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(28)); r16_29 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(29)); r16_30 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(30)); r16_31 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r16(31)); r15_0 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r15(0)); r15_1 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r15(1)); r15_2 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r15(2)); r15_3 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r15(3)); r15_4 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r15(4)); r15_5 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r15(5)); r15_6 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r15(6)); r15_7 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r15(7)); r15_8 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r15(8)); r15_9 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r15(9)); r15_10 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r15(10)); r15_11 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r15(11)); r15_12 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r15(12)); r15_13 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r15(13)); r15_14 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r15(14)); r15_15 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r15(15), i1 => p(0), i0 => q(15)); r15_16 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r15(16), i1 => p(1), i0 => q(15)); r15_17 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r15(17), i1 => p(2), i0 => q(15)); r15_18 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r15(18), i1 => p(3), i0 => q(15)); r15_19 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r15(19), i1 => p(4), i0 => q(15)); r15_20 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r15(20), i1 => p(5), i0 => q(15)); r15_21 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r15(21), i1 => p(6), i0 => q(15)); r15_22 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r15(22), i1 => p(7), i0 => q(15)); r15_23 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r15(23), i1 => p(8), i0 => q(15)); r15_24 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r15(24), i1 => p(9), i0 => q(15)); r15_25 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r15(25), i1 => p(10), i0 => q(15)); r15_26 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r15(26), i1 => p(11), i0 => q(15)); r15_27 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r15(27), i1 => p(12), i0 => q(15)); r15_28 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r15(28), i1 => p(13), i0 => q(15)); r15_29 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r15(29), i1 => p(14), i0 => q(15)); r15_30 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r15(30), i1 => p(15), i0 => q(15)); r15_31 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r15(31), i1 => p(16), i0 => q(15)); r14_0 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r14(0)); r14_1 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r14(1)); r14_2 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r14(2)); r14_3 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r14(3)); r14_4 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r14(4)); r14_5 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r14(5)); r14_6 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r14(6)); r14_7 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r14(7)); r14_8 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r14(8)); r14_9 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r14(9)); r14_10 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r14(10)); r14_11 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r14(11)); r14_12 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r14(12)); r14_13 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r14(13)); r14_14 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r14(14), i1 => p(0), i0 => q(14)); r14_15 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r14(15), i1 => p(1), i0 => q(14)); r14_16 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r14(16), i1 => p(2), i0 => q(14)); r14_17 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r14(17), i1 => p(3), i0 => q(14)); r14_18 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r14(18), i1 => p(4), i0 => q(14)); r14_19 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r14(19), i1 => p(5), i0 => q(14)); r14_20 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r14(20), i1 => p(6), i0 => q(14)); r14_21 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r14(21), i1 => p(7), i0 => q(14)); r14_22 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r14(22), i1 => p(8), i0 => q(14)); r14_23 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r14(23), i1 => p(9), i0 => q(14)); r14_24 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r14(24), i1 => p(10), i0 => q(14)); r14_25 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r14(25), i1 => p(11), i0 => q(14)); r14_26 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r14(26), i1 => p(12), i0 => q(14)); r14_27 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r14(27), i1 => p(13), i0 => q(14)); r14_28 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r14(28), i1 => p(14), i0 => q(14)); r14_29 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r14(29), i1 => p(15), i0 => q(14)); r14_30 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r14(30), i1 => p(16), i0 => q(14)); r14_31 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r14(31)); r13_0 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r13(0)); r13_1 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r13(1)); r13_2 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r13(2)); r13_3 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r13(3)); r13_4 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r13(4)); r13_5 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r13(5)); r13_6 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r13(6)); r13_7 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r13(7)); r13_8 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r13(8)); r13_9 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r13(9)); r13_10 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r13(10)); r13_11 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r13(11)); r13_12 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r13(12)); r13_13 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r13(13), i1 => p(0), i0 => q(13)); r13_14 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r13(14), i1 => p(1), i0 => q(13)); r13_15 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r13(15), i1 => p(2), i0 => q(13)); r13_16 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r13(16), i1 => p(3), i0 => q(13)); r13_17 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r13(17), i1 => p(4), i0 => q(13)); r13_18 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r13(18), i1 => p(5), i0 => q(13)); r13_19 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r13(19), i1 => p(6), i0 => q(13)); r13_20 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r13(20), i1 => p(7), i0 => q(13)); r13_21 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r13(21), i1 => p(8), i0 => q(13)); r13_22 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r13(22), i1 => p(9), i0 => q(13)); r13_23 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r13(23), i1 => p(10), i0 => q(13)); r13_24 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r13(24), i1 => p(11), i0 => q(13)); r13_25 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r13(25), i1 => p(12), i0 => q(13)); r13_26 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r13(26), i1 => p(13), i0 => q(13)); r13_27 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r13(27), i1 => p(14), i0 => q(13)); r13_28 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r13(28), i1 => p(15), i0 => q(13)); r13_29 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r13(29), i1 => p(16), i0 => q(13)); r13_30 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r13(30)); r13_31 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r13(31)); r12_0 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r12(0)); r12_1 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r12(1)); r12_2 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r12(2)); r12_3 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r12(3)); r12_4 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r12(4)); r12_5 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r12(5)); r12_6 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r12(6)); r12_7 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r12(7)); r12_8 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r12(8)); r12_9 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r12(9)); r12_10 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r12(10)); r12_11 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r12(11)); r12_12 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r12(12), i1 => p(0), i0 => q(12)); r12_13 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r12(13), i1 => p(1), i0 => q(12)); r12_14 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r12(14), i1 => p(2), i0 => q(12)); r12_15 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r12(15), i1 => p(3), i0 => q(12)); r12_16 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r12(16), i1 => p(4), i0 => q(12)); r12_17 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r12(17), i1 => p(5), i0 => q(12)); r12_18 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r12(18), i1 => p(6), i0 => q(12)); r12_19 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r12(19), i1 => p(7), i0 => q(12)); r12_20 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r12(20), i1 => p(8), i0 => q(12)); r12_21 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r12(21), i1 => p(9), i0 => q(12)); r12_22 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r12(22), i1 => p(10), i0 => q(12)); r12_23 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r12(23), i1 => p(11), i0 => q(12)); r12_24 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r12(24), i1 => p(12), i0 => q(12)); r12_25 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r12(25), i1 => p(13), i0 => q(12)); r12_26 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r12(26), i1 => p(14), i0 => q(12)); r12_27 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r12(27), i1 => p(15), i0 => q(12)); r12_28 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r12(28), i1 => p(16), i0 => q(12)); r12_29 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r12(29)); r12_30 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r12(30)); r12_31 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r12(31)); r11_0 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r11(0)); r11_1 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r11(1)); r11_2 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r11(2)); r11_3 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r11(3)); r11_4 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r11(4)); r11_5 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r11(5)); r11_6 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r11(6)); r11_7 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r11(7)); r11_8 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r11(8)); r11_9 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r11(9)); r11_10 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r11(10)); r11_11 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r11(11), i1 => p(0), i0 => q(11)); r11_12 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r11(12), i1 => p(1), i0 => q(11)); r11_13 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r11(13), i1 => p(2), i0 => q(11)); r11_14 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r11(14), i1 => p(3), i0 => q(11)); r11_15 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r11(15), i1 => p(4), i0 => q(11)); r11_16 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r11(16), i1 => p(5), i0 => q(11)); r11_17 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r11(17), i1 => p(6), i0 => q(11)); r11_18 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r11(18), i1 => p(7), i0 => q(11)); r11_19 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r11(19), i1 => p(8), i0 => q(11)); r11_20 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r11(20), i1 => p(9), i0 => q(11)); r11_21 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r11(21), i1 => p(10), i0 => q(11)); r11_22 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r11(22), i1 => p(11), i0 => q(11)); r11_23 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r11(23), i1 => p(12), i0 => q(11)); r11_24 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r11(24), i1 => p(13), i0 => q(11)); r11_25 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r11(25), i1 => p(14), i0 => q(11)); r11_26 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r11(26), i1 => p(15), i0 => q(11)); r11_27 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r11(27), i1 => p(16), i0 => q(11)); r11_28 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r11(28)); r11_29 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r11(29)); r11_30 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r11(30)); r11_31 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r11(31)); r10_0 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r10(0)); r10_1 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r10(1)); r10_2 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r10(2)); r10_3 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r10(3)); r10_4 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r10(4)); r10_5 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r10(5)); r10_6 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r10(6)); r10_7 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r10(7)); r10_8 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r10(8)); r10_9 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r10(9)); r10_10 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r10(10), i1 => p(0), i0 => q(10)); r10_11 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r10(11), i1 => p(1), i0 => q(10)); r10_12 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r10(12), i1 => p(2), i0 => q(10)); r10_13 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r10(13), i1 => p(3), i0 => q(10)); r10_14 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r10(14), i1 => p(4), i0 => q(10)); r10_15 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r10(15), i1 => p(5), i0 => q(10)); r10_16 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r10(16), i1 => p(6), i0 => q(10)); r10_17 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r10(17), i1 => p(7), i0 => q(10)); r10_18 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r10(18), i1 => p(8), i0 => q(10)); r10_19 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r10(19), i1 => p(9), i0 => q(10)); r10_20 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r10(20), i1 => p(10), i0 => q(10)); r10_21 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r10(21), i1 => p(11), i0 => q(10)); r10_22 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r10(22), i1 => p(12), i0 => q(10)); r10_23 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r10(23), i1 => p(13), i0 => q(10)); r10_24 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r10(24), i1 => p(14), i0 => q(10)); r10_25 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r10(25), i1 => p(15), i0 => q(10)); r10_26 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r10(26), i1 => p(16), i0 => q(10)); r10_27 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r10(27)); r10_28 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r10(28)); r10_29 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r10(29)); r10_30 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r10(30)); r10_31 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r10(31)); r9_0 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r9(0)); r9_1 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r9(1)); r9_2 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r9(2)); r9_3 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r9(3)); r9_4 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r9(4)); r9_5 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r9(5)); r9_6 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r9(6)); r9_7 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r9(7)); r9_8 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r9(8)); r9_9 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r9(9), i1 => p(0), i0 => q(9)); r9_10 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r9(10), i1 => p(1), i0 => q(9)); r9_11 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r9(11), i1 => p(2), i0 => q(9)); r9_12 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r9(12), i1 => p(3), i0 => q(9)); r9_13 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r9(13), i1 => p(4), i0 => q(9)); r9_14 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r9(14), i1 => p(5), i0 => q(9)); r9_15 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r9(15), i1 => p(6), i0 => q(9)); r9_16 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r9(16), i1 => p(7), i0 => q(9)); r9_17 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r9(17), i1 => p(8), i0 => q(9)); r9_18 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r9(18), i1 => p(9), i0 => q(9)); r9_19 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r9(19), i1 => p(10), i0 => q(9)); r9_20 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r9(20), i1 => p(11), i0 => q(9)); r9_21 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r9(21), i1 => p(12), i0 => q(9)); r9_22 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r9(22), i1 => p(13), i0 => q(9)); r9_23 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r9(23), i1 => p(14), i0 => q(9)); r9_24 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r9(24), i1 => p(15), i0 => q(9)); r9_25 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r9(25), i1 => p(16), i0 => q(9)); r9_26 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r9(26)); r9_27 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r9(27)); r9_28 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r9(28)); r9_29 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r9(29)); r9_30 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r9(30)); r9_31 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r9(31)); r8_0 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r8(0)); r8_1 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r8(1)); r8_2 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r8(2)); r8_3 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r8(3)); r8_4 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r8(4)); r8_5 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r8(5)); r8_6 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r8(6)); r8_7 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r8(7)); r8_8 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r8(8), i1 => p(0), i0 => q(8)); r8_9 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r8(9), i1 => p(1), i0 => q(8)); r8_10 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r8(10), i1 => p(2), i0 => q(8)); r8_11 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r8(11), i1 => p(3), i0 => q(8)); r8_12 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r8(12), i1 => p(4), i0 => q(8)); r8_13 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r8(13), i1 => p(5), i0 => q(8)); r8_14 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r8(14), i1 => p(6), i0 => q(8)); r8_15 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r8(15), i1 => p(7), i0 => q(8)); r8_16 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r8(16), i1 => p(8), i0 => q(8)); r8_17 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r8(17), i1 => p(9), i0 => q(8)); r8_18 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r8(18), i1 => p(10), i0 => q(8)); r8_19 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r8(19), i1 => p(11), i0 => q(8)); r8_20 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r8(20), i1 => p(12), i0 => q(8)); r8_21 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r8(21), i1 => p(13), i0 => q(8)); r8_22 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r8(22), i1 => p(14), i0 => q(8)); r8_23 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r8(23), i1 => p(15), i0 => q(8)); r8_24 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r8(24), i1 => p(16), i0 => q(8)); r8_25 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r8(25)); r8_26 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r8(26)); r8_27 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r8(27)); r8_28 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r8(28)); r8_29 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r8(29)); r8_30 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r8(30)); r8_31 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r8(31)); r7_0 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r7(0)); r7_1 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r7(1)); r7_2 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r7(2)); r7_3 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r7(3)); r7_4 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r7(4)); r7_5 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r7(5)); r7_6 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r7(6)); r7_7 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r7(7), i1 => p(0), i0 => q(7)); r7_8 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r7(8), i1 => p(1), i0 => q(7)); r7_9 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r7(9), i1 => p(2), i0 => q(7)); r7_10 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r7(10), i1 => p(3), i0 => q(7)); r7_11 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r7(11), i1 => p(4), i0 => q(7)); r7_12 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r7(12), i1 => p(5), i0 => q(7)); r7_13 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r7(13), i1 => p(6), i0 => q(7)); r7_14 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r7(14), i1 => p(7), i0 => q(7)); r7_15 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r7(15), i1 => p(8), i0 => q(7)); r7_16 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r7(16), i1 => p(9), i0 => q(7)); r7_17 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r7(17), i1 => p(10), i0 => q(7)); r7_18 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r7(18), i1 => p(11), i0 => q(7)); r7_19 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r7(19), i1 => p(12), i0 => q(7)); r7_20 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r7(20), i1 => p(13), i0 => q(7)); r7_21 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r7(21), i1 => p(14), i0 => q(7)); r7_22 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r7(22), i1 => p(15), i0 => q(7)); r7_23 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r7(23), i1 => p(16), i0 => q(7)); r7_24 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r7(24)); r7_25 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r7(25)); r7_26 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r7(26)); r7_27 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r7(27)); r7_28 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r7(28)); r7_29 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r7(29)); r7_30 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r7(30)); r7_31 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r7(31)); r6_0 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r6(0)); r6_1 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r6(1)); r6_2 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r6(2)); r6_3 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r6(3)); r6_4 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r6(4)); r6_5 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r6(5)); r6_6 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r6(6), i1 => p(0), i0 => q(6)); r6_7 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r6(7), i1 => p(1), i0 => q(6)); r6_8 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r6(8), i1 => p(2), i0 => q(6)); r6_9 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r6(9), i1 => p(3), i0 => q(6)); r6_10 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r6(10), i1 => p(4), i0 => q(6)); r6_11 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r6(11), i1 => p(5), i0 => q(6)); r6_12 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r6(12), i1 => p(6), i0 => q(6)); r6_13 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r6(13), i1 => p(7), i0 => q(6)); r6_14 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r6(14), i1 => p(8), i0 => q(6)); r6_15 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r6(15), i1 => p(9), i0 => q(6)); r6_16 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r6(16), i1 => p(10), i0 => q(6)); r6_17 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r6(17), i1 => p(11), i0 => q(6)); r6_18 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r6(18), i1 => p(12), i0 => q(6)); r6_19 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r6(19), i1 => p(13), i0 => q(6)); r6_20 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r6(20), i1 => p(14), i0 => q(6)); r6_21 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r6(21), i1 => p(15), i0 => q(6)); r6_22 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r6(22), i1 => p(16), i0 => q(6)); r6_23 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r6(23)); r6_24 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r6(24)); r6_25 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r6(25)); r6_26 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r6(26)); r6_27 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r6(27)); r6_28 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r6(28)); r6_29 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r6(29)); r6_30 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r6(30)); r6_31 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r6(31)); r5_0 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r5(0)); r5_1 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r5(1)); r5_2 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r5(2)); r5_3 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r5(3)); r5_4 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r5(4)); r5_5 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r5(5), i1 => p(0), i0 => q(5)); r5_6 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r5(6), i1 => p(1), i0 => q(5)); r5_7 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r5(7), i1 => p(2), i0 => q(5)); r5_8 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r5(8), i1 => p(3), i0 => q(5)); r5_9 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r5(9), i1 => p(4), i0 => q(5)); r5_10 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r5(10), i1 => p(5), i0 => q(5)); r5_11 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r5(11), i1 => p(6), i0 => q(5)); r5_12 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r5(12), i1 => p(7), i0 => q(5)); r5_13 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r5(13), i1 => p(8), i0 => q(5)); r5_14 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r5(14), i1 => p(9), i0 => q(5)); r5_15 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r5(15), i1 => p(10), i0 => q(5)); r5_16 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r5(16), i1 => p(11), i0 => q(5)); r5_17 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r5(17), i1 => p(12), i0 => q(5)); r5_18 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r5(18), i1 => p(13), i0 => q(5)); r5_19 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r5(19), i1 => p(14), i0 => q(5)); r5_20 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r5(20), i1 => p(15), i0 => q(5)); r5_21 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r5(21), i1 => p(16), i0 => q(5)); r5_22 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r5(22)); r5_23 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r5(23)); r5_24 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r5(24)); r5_25 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r5(25)); r5_26 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r5(26)); r5_27 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r5(27)); r5_28 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r5(28)); r5_29 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r5(29)); r5_30 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r5(30)); r5_31 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r5(31)); r4_0 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r4(0)); r4_1 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r4(1)); r4_2 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r4(2)); r4_3 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r4(3)); r4_4 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r4(4), i1 => p(0), i0 => q(4)); r4_5 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r4(5), i1 => p(1), i0 => q(4)); r4_6 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r4(6), i1 => p(2), i0 => q(4)); r4_7 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r4(7), i1 => p(3), i0 => q(4)); r4_8 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r4(8), i1 => p(4), i0 => q(4)); r4_9 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r4(9), i1 => p(5), i0 => q(4)); r4_10 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r4(10), i1 => p(6), i0 => q(4)); r4_11 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r4(11), i1 => p(7), i0 => q(4)); r4_12 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r4(12), i1 => p(8), i0 => q(4)); r4_13 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r4(13), i1 => p(9), i0 => q(4)); r4_14 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r4(14), i1 => p(10), i0 => q(4)); r4_15 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r4(15), i1 => p(11), i0 => q(4)); r4_16 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r4(16), i1 => p(12), i0 => q(4)); r4_17 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r4(17), i1 => p(13), i0 => q(4)); r4_18 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r4(18), i1 => p(14), i0 => q(4)); r4_19 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r4(19), i1 => p(15), i0 => q(4)); r4_20 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r4(20), i1 => p(16), i0 => q(4)); r4_21 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r4(21)); r4_22 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r4(22)); r4_23 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r4(23)); r4_24 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r4(24)); r4_25 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r4(25)); r4_26 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r4(26)); r4_27 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r4(27)); r4_28 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r4(28)); r4_29 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r4(29)); r4_30 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r4(30)); r4_31 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r4(31)); r3_0 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r3(0)); r3_1 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r3(1)); r3_2 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r3(2)); r3_3 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r3(3), i1 => p(0), i0 => q(3)); r3_4 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r3(4), i1 => p(1), i0 => q(3)); r3_5 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r3(5), i1 => p(2), i0 => q(3)); r3_6 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r3(6), i1 => p(3), i0 => q(3)); r3_7 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r3(7), i1 => p(4), i0 => q(3)); r3_8 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r3(8), i1 => p(5), i0 => q(3)); r3_9 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r3(9), i1 => p(6), i0 => q(3)); r3_10 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r3(10), i1 => p(7), i0 => q(3)); r3_11 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r3(11), i1 => p(8), i0 => q(3)); r3_12 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r3(12), i1 => p(9), i0 => q(3)); r3_13 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r3(13), i1 => p(10), i0 => q(3)); r3_14 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r3(14), i1 => p(11), i0 => q(3)); r3_15 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r3(15), i1 => p(12), i0 => q(3)); r3_16 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r3(16), i1 => p(13), i0 => q(3)); r3_17 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r3(17), i1 => p(14), i0 => q(3)); r3_18 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r3(18), i1 => p(15), i0 => q(3)); r3_19 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r3(19), i1 => p(16), i0 => q(3)); r3_20 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r3(20)); r3_21 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r3(21)); r3_22 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r3(22)); r3_23 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r3(23)); r3_24 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r3(24)); r3_25 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r3(25)); r3_26 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r3(26)); r3_27 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r3(27)); r3_28 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r3(28)); r3_29 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r3(29)); r3_30 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r3(30)); r3_31 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r3(31)); r2_0 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r2(0)); r2_1 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r2(1)); r2_2 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r2(2), i1 => p(0), i0 => q(2)); r2_3 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r2(3), i1 => p(1), i0 => q(2)); r2_4 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r2(4), i1 => p(2), i0 => q(2)); r2_5 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r2(5), i1 => p(3), i0 => q(2)); r2_6 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r2(6), i1 => p(4), i0 => q(2)); r2_7 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r2(7), i1 => p(5), i0 => q(2)); r2_8 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r2(8), i1 => p(6), i0 => q(2)); r2_9 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r2(9), i1 => p(7), i0 => q(2)); r2_10 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r2(10), i1 => p(8), i0 => q(2)); r2_11 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r2(11), i1 => p(9), i0 => q(2)); r2_12 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r2(12), i1 => p(10), i0 => q(2)); r2_13 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r2(13), i1 => p(11), i0 => q(2)); r2_14 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r2(14), i1 => p(12), i0 => q(2)); r2_15 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r2(15), i1 => p(13), i0 => q(2)); r2_16 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r2(16), i1 => p(14), i0 => q(2)); r2_17 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r2(17), i1 => p(15), i0 => q(2)); r2_18 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r2(18), i1 => p(16), i0 => q(2)); r2_19 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r2(19)); r2_20 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r2(20)); r2_21 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r2(21)); r2_22 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r2(22)); r2_23 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r2(23)); r2_24 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r2(24)); r2_25 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r2(25)); r2_26 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r2(26)); r2_27 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r2(27)); r2_28 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r2(28)); r2_29 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r2(29)); r2_30 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r2(30)); r2_31 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r2(31)); r1_0 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r1(0)); r1_1 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r1(1), i1 => p(0), i0 => q(1)); r1_2 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r1(2), i1 => p(1), i0 => q(1)); r1_3 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r1(3), i1 => p(2), i0 => q(1)); r1_4 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r1(4), i1 => p(3), i0 => q(1)); r1_5 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r1(5), i1 => p(4), i0 => q(1)); r1_6 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r1(6), i1 => p(5), i0 => q(1)); r1_7 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r1(7), i1 => p(6), i0 => q(1)); r1_8 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r1(8), i1 => p(7), i0 => q(1)); r1_9 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r1(9), i1 => p(8), i0 => q(1)); r1_10 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r1(10), i1 => p(9), i0 => q(1)); r1_11 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r1(11), i1 => p(10), i0 => q(1)); r1_12 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r1(12), i1 => p(11), i0 => q(1)); r1_13 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r1(13), i1 => p(12), i0 => q(1)); r1_14 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r1(14), i1 => p(13), i0 => q(1)); r1_15 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r1(15), i1 => p(14), i0 => q(1)); r1_16 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r1(16), i1 => p(15), i0 => q(1)); r1_17 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r1(17), i1 => p(16), i0 => q(1)); r1_18 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r1(18)); r1_19 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r1(19)); r1_20 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r1(20)); r1_21 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r1(21)); r1_22 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r1(22)); r1_23 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r1(23)); r1_24 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r1(24)); r1_25 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r1(25)); r1_26 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r1(26)); r1_27 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r1(27)); r1_28 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r1(28)); r1_29 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r1(29)); r1_30 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r1(30)); r1_31 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r1(31)); r0_0 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r0(0), i1 => p(0), i0 => q(0)); r0_1 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r0(1), i1 => p(1), i0 => q(0)); r0_2 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r0(2), i1 => p(2), i0 => q(0)); r0_3 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r0(3), i1 => p(3), i0 => q(0)); r0_4 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r0(4), i1 => p(4), i0 => q(0)); r0_5 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r0(5), i1 => p(5), i0 => q(0)); r0_6 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r0(6), i1 => p(6), i0 => q(0)); r0_7 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r0(7), i1 => p(7), i0 => q(0)); r0_8 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r0(8), i1 => p(8), i0 => q(0)); r0_9 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r0(9), i1 => p(9), i0 => q(0)); r0_10 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r0(10), i1 => p(10), i0 => q(0)); r0_11 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r0(11), i1 => p(11), i0 => q(0)); r0_12 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r0(12), i1 => p(12), i0 => q(0)); r0_13 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r0(13), i1 => p(13), i0 => q(0)); r0_14 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r0(14), i1 => p(14), i0 => q(0)); r0_15 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r0(15), i1 => p(15), i0 => q(0)); r0_16 : a2_x2 PORT MAP ( vss => vss, vdd => vdd, q => r0(16), i1 => p(16), i0 => q(0)); r0_17 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r0(17)); r0_18 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r0(18)); r0_19 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r0(19)); r0_20 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r0(20)); r0_21 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r0(21)); r0_22 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r0(22)); r0_23 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r0(23)); r0_24 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r0(24)); r0_25 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r0(25)); r0_26 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r0(26)); r0_27 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r0(27)); r0_28 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r0(28)); r0_29 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r0(29)); r0_30 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r0(30)); r0_31 : zero_x0 PORT MAP ( vss => vss, vdd => vdd, nq => r0(31)); end VST; @ 1.1.1.1 log @no message @ text @@