head 1.3; access; symbols initial_import:1.1.1.1 pci_blue_interface:1.1.1; locks; strict; comment @# @; 1.3 date 2001.07.06.10.50.59; author bbeaver; state Exp; branches; next 1.2; 1.2 date 2001.06.08.08.48.25; author bbeaver; state Exp; branches; next 1.1; 1.1 date 2001.02.21.15.27.29; author bbeaver; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2001.02.21.15.27.29; author bbeaver; state Exp; branches; next ; desc @@ 1.3 log @Massive edit to start changing many `defines into Parameters. This MIGHT (?) make it possible to have more than 1 PCI interface, but with different bus sizes. On the other hand, it might be an idiotic change in style. @ text @ 498 60 50 50 @ 1.2 log @Working on pci_blue_master Adding state machine and carefully crafted FRAME and IRDY next value function This code compiles, but does not function at all The previous version should be used when exploring the test framework. @ text @d4 1 a4 1 150 d9 1 @ 1.1 log @Initial revision @ text @d3 1 a3 1 @ 1.1.1.1 log @Initial Import of pci_blue_interface Only the behaviorial code works There is no synthesizable code in this initial source import @ text @@