The terminology used reflects the data flow.
For example, `pavr_s4_s6_rfwr_addr1' is assigned in s3 (by the instruction decoder), shifts into `pavr_s5_s6_rfwr_addr1', that finally shifts into `pavr_s6_rfwr_addr1' (terminal register). Only this one carries information actually used by hardware resource managers. This particualr one signalizes an access request to the Register File write port manager.
Process splitting strategy:
requests to hardware resources are managed by dedicated processes, one VHDL process per hardware resource.
a main asynchronous process (instruction decoder) computes values that initialize the pipeline in s3.
a main synchronous process assings new values to pipeline registers.