head 1.1; branch 1.1.1; access ; symbols noReleaseTag: noVendorName:1.1.1; locks ; strict; comment @# @; 1.1 date 2003.; author doru; state Exp; branches; next ; date 2003.; author doru; state Exp; branches ; next ; desc @@ 1.1 log @Initial revision @ text @ Skips
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[Pipeline details]

A few details
Skips are implemented as branches that have the relative target address equal to 0, 1 or 2, depending on the skip condition and on whether the following instruction has 16 or 32 bits.
There are two kinds of skips: one category that makes the skip request in stage s6 (the same as branches), and one that requests skip in s61. The first category includes instructions CPSE (Compare registers and skip if equal), SBRC and SBRS (skip if bit in register is cleared/set). The second category includes SBIC, SBIS (Skip if bit in IO register is cleared/set).

CPSE, SBRC and SBRS take 2 clocks if not taken, and 4 clocks if taken.
SBIC and SBIS take 3 clocks if not taken, and 5 clocks if taken.
Skip state machine


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