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Stall and Flush Unit
[Hardware resources]

The pipeline controls its own stall and flush status, through specific stall and flush-related request signals. These requests are sent to the Stall and Flush Unit (SFU). The output of the SFU is a set of signals that directly control pipeline stages (a stall and flush control signals pair for each stage):

pavr_hwres_sfu_01.gif

Requests to SFU
SFU control signals
Each main pipeline stage (s1-s6) has 2 kinds of control signals, that are generated by the SFU:
Each main pipeline stage has an associated flag that determines whether or not that stage has the right to access hardware resources. These flags are also managed by the SFU.
Hardware resources enabling flags:

Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by doxygen1.2.16
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