External interrupt 0 is physically mapped on the line 0 (bit 0) of port A.
Its associated interrupt flag resides into the IO File register GIFR (General Interrupt Flags Register):
External interrupt 0 is enabled/disabled by setting/clearing bit 6 in GIMSK (General Interrupt Mask) register:
If enabled, it can trigger an interrupt on high-to-low transition, low-to-high transition, or on a low level of the interrupt 0 input. This behavior is defined by 2 bits in the MCUCR (Microcontroller Control) register:
Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by
@Importing into repository the new directory structure.