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Bypass Unit
[Hardware resources]


Modules

Bypass chain 0
Bypass chain 1
Bypass chain 2

Detailed Description

General considerations
The Bypass Unit (BPU) is a FIFO-like temporary storage area, that keeps data to be written into the Register File.
If an instruction computes a value that must be written into the Register File (RF) (an ALU instruction, for example) it first writes the BPU, and then (or at the same time) actually writes the RF.
If the following instructions need an operand from the RF, at the same address where the previous result should have been written into the RF, they will actually read that operand from the BPU rather than from RF.
This way, `read before write' pipeline hazards are avoided.

The specific situations where BPU is needed are:
Details
The algorithm of using BPU:
The maximum delay between a write and a read from the RF is 4 clocks. Thus, the BPU FIFO-like structure has a depth of 4.
On the other hand, the BPU must be able to be written 3 one byte operands, at a time (must have 3 write ports). The most BPU demanding instructions are stores with pre(post) decrement(increment). Both the one byte data and a 2 byte pointer register must be written into the BPU, as well as into the RF. The 3 bytes are simultaneousely written into so-called `BPU chains' or `BPU registers' (BPU chains 0, 1, 2; or BPU registers 0, 1, 2; or BPR0, BPR1, BPR2).

The BPU has 3x4 entries, each consisting of:
Accessing BPU:

pavr_hwres_bpu_01.gif



Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by doxygen1.2.16
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