head 1.1; access; symbols rel-0-3-0-rc1:1.1; locks; strict; comment @# @; 1.1 date 2008.10.12.17.27.52; author jeremybennett; state Exp; branches; next ; commitid 6d5848f2328c4567; desc @@ 1.1 log @These are all the changes for Or1ksim 0.3.0 release candidate 1. The changes are explained in the NEWS, README and ChangeLog files. A number of long-standing bugs are fixed (see the OpenRISC tracker), and the code is brought up to a consistent standard, following the GNU coding conventions throughout. Argument parsing now uses argtable2, and a User Guide has been added. Documentation throughout has been extended to be compatible with Doxygen, providing a further level of technical detail on the internals. @ text @/* debug.cfg -- Simulator configuration script file with debug enabled Copyright (C) 2001-2002, Marko Mlinar, markom@@opencores.org This file is part of OpenRISC 1000 Architectural Simulator. It contains the default configuration and help about configuring the simulator. This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ /* INTRODUCTION The ork1sim has various parameters, that are set in configuration files like this one. The user can switch between configurations at startup by specifying the required configuration file with the -f option. If no configuration file is specified or1ksim searches for the default configuration file sim.cfg. First it searches for './sim.cfg'. If this file is not found, it searches for '~/or1k/sim.cfg'. If this file is not found too, it reverts to the built-in default configuration. NOTE: Users should not rely on the built-in configuration, since the default configuration may differ between version. Rather create a configuration file that sets all critical values. This file may contain (standard C) comments only - no // support. Configure files may be be included, using: include "file_name_to_include" Like normal configuration files, the included file is divided into sections. Each section is described in detail also. Some section have subsections. One example of such a subsection is: device instance specific parameters... enddevice which creates a device instance. */ /* MEMORY SECTION This section specifies how the memory is generated and the blocks it consists of. type = random/unknown/pattern Specifies the initial memory values. 'random' generates random memory using seed 'random_seed'. 'pattern' fills memory with 'pattern'. 'unknown' does not specify how memory should be generated, leaving the memory in a undefined state. This is the fastest option. random_seed = random seed for randomizer, used if type = 'random'. pattern = pattern to fill memory, used if type = 'pattern'. baseaddr = memory start address size = memory size name = "" memory block name ce = chip enable index of the memory instance mc = memory controller this memory is connected to delayr = cycles, required for read access, -1 if instance does not support reading delayw = cycles, required for write access, -1 if instance does not support writing log = "" filename, where to log memory accesses to. If log command is not specified, accesses are not logged. */ section memory name = "RAM" random_seed = -1 type = random ce = 0 mc = 0 baseaddr = 0x00000000 size = 0x00400000 delayr = 1 delayw = 2 end /* IMMU SECTION This section configures the Instruction Memory Manangement Unit enabled = 0/1 '0': disabled '1': enabled (NOTE: UPR bit is set) nsets = number of ITLB sets; must be power of two nways = number of ITLB ways pagesize = instruction page size; must be power of two entrysize = instruction entry size in bytes ustates = number of ITLB usage states (2, 3, 4 etc., max is 4) hitdelay = number of cycles immu hit costs missdelay = number of cycles immu miss costs */ section immu enabled = 0 nsets = 64 nways = 1 pagesize = 8192 hitdelay = 0 missdelay = 0 end /* DMMU SECTION This section configures the Data Memory Manangement Unit enabled = 0/1 '0': disabled '1': enabled (NOTE: UPR bit is set) nsets = number of DTLB sets; must be power of two nways = number of DTLB ways pagesize = data page size; must be power of two entrysize = data entry size in bytes ustates = number of DTLB usage states (2, 3, 4 etc., max is 4) hitdelay = number of cycles dmmu hit costs missdelay = number of cycles dmmu miss costs */ section dmmu enabled = 0 nsets = 64 nways = 1 pagesize = 8192 hitdelay = 0 missdelay = 0 end /* IC SECTION This section configures the Instruction Cache enabled = 0/1 '0': disabled '1': enabled (NOTE: UPR bit is set) nsets = number of IC sets; must be power of two nways = number of IC ways blocksize = IC block size in bytes; must be power of two ustates = number of IC usage states (2, 3, 4 etc., max is 4) hitdelay = number of cycles ic hit costs missdelay = number of cycles ic miss costs */ section ic enabled = 0 nsets = 256 nways = 1 blocksize = 16 hitdelay = 0 missdelay = 0 end /* DC SECTION This section configures the Data Cache enabled = 0/1 '0': disabled '1': enabled (NOTE: UPR bit is set) nsets = number of DC sets; must be power of two nways = number of DC ways blocksize = DC block size in bytes; must be power of two ustates = number of DC usage states (2, 3, 4 etc., max is 4) load_hitdelay = number of cycles dc load hit costs load_missdelay = number of cycles dc load miss costs store_hitdelay = number of cycles dc store hit costs store_missdelay = number of cycles dc store miss costs */ section dc enabled = 0 nsets = 256 nways = 1 blocksize = 16 load_hitdelay = 0 load_missdelay = 0 store_hitdelay = 0 store_missdelay = 0 end /* PIC SECTION This section specifies how the pic should behave enabled = 0/1 '0': PIC is disabled '1': PIC is enabled edge_trigger = 0/1 '0': Level triggered PIC '1': Edge triggered PIC */ section pic enabled = 0 edge_trigger = 1 end /* SIM SECTION This section specifies how or1ksim should behave. verbose = 0/1 '0': don't print extra messages '1': print extra messages debug = 0-9 0 : no debug messages 1-9: debug message level. higher numbers produce more messages profile = 0/1 '0': don't generate profiling file 'sim.profile' '1': don't generate profiling file 'sim.profile' prof_file = "" optional filename for the profiling file. valid only if 'profile' is set mprofile = 0/1 '0': don't generate memory profiling file 'sim.mprofile' '1': generate memory profiling file 'sim.mprofile' mprof_file = "" optional filename for the memory profiling file. valid only if 'mprofile' is set history = 0/1 '0': don't track execution flow '1': track execution flow Execution flow can be tracked for the simulator's 'hist' command. Useful for back-trace debugging. iprompt = 0/1 '0': start in (so what do we start in ???) '1': start in interactive prompt. exe_log = 0/1 '0': don't generate execution log. '1': generate execution log. exe_log_type = default/hardware/simple/software type of execution log, default is used when not specified exe_log_start = index of first instruction to start logging, default = 0 exe_log_end = index of last instruction to end logging; not limited, if omitted exe_log_marker = specifies number of instructions before horizontal marker is printed; if zero, markers are disabled (default) exe_log_file = "" filename for the exection log file. valid only if 'exe_log' is set clkcycle = [ps|ns|us|ms] specifies time measurement for one cycle */ section sim /* verbose = 1 */ debug = 0 profile = 0 prof_file = "sim.profile" history = 0 /* iprompt = 0 */ exe_log = 0 exe_log_type = software exe_log_start = 0 /* exe_log_end = 20000000*/ exe_log_marker = 10000 exe_log_file = "executed.log" clkcycle = 100ns end /* SECTION VAPI This section configures the Verification API, used for Advanced Core Verification. enabled = 0/1 '0': disbable VAPI server '1': enable/start VAPI server server_port = TCP/IP port to start VAPI server on log_enabled = 0/1 '0': disable VAPI requests logging '1': enable VAPI requests logging hide_device_id = 0/1 '1': don't log device id (for compatability with old version) '0': log device id vapi_log_file = filename for the log file. valid only if log_enabled is set */ section VAPI enabled = 0 server_port = 50000 log_enabled = 0 vapi_log_file = "vapi.log" end /* CPU SECTION This section specifies various CPU parameters. ver = cfg = rev = specifies version, configuration and revision fields of the CPU version register. upr = changes the upr register cfgr = changes the CPU configuration register sr = sets the initial Supervision Register value superscalar = 0/1 '0': CPU is scalar '1': CPU is superscalar (modify cpu/or32/execute.c to tune superscalar model) hazards = 0/1 '0': don't track data hazards in superscalar CPU '1': track data hazards in superscalar CPU If tracked, data hazards can be displayed using the simulator's 'r' command. dependstats = 0/1 '0': don't calculate inter-instruction dependencies. '1': calculate inter-instruction dependencies. If calculated, inter-instruction dependencies can be displayed using the simulator's 'stat' command. sbuf_len = length of store buffer (<= 256), 0 = disabled */ section cpu ver = 0x12 cfg = 0x00 rev = 0x0001 superscalar = 0 hazards = 0 dependstats = 0 sbuf_len = 0 end /* PM SECTION This section specifies Power Management parameters enabled = 0/1 '0': disable power management '1': enable power management */ section pm enabled = 0 end /* BPB SECTION This section specifies how branch prediction should behave. enabled = 0/1 '0': disable branch prediction '1': enable branch prediction btic = 0/1 '0': disable branch target instruction cache model '1': enable branch target instruction cache model sbp_bf_fwd = 0/1 Static branch prediction for 'l.bf' '0': don't use forward prediction '1': use forward prediction sbp_bnf_fwd = 0/1 Static branch prediction for 'l.bnf' '0': don't use forward prediction '1': use forward prediction hitdelay = number of cycles bpb hit costs missdelay = number of cycles bpb miss costs */ section bpb enabled = 0 btic = 0 sbp_bf_fwd = 0 sbp_bnf_fwd = 0 hitdelay = 0 missdelay = 0 end /* DEBUG SECTION This sections specifies how the debug unit should behave. enabled = 0/1 '0': disable debug unit '1': enable debug unit gdb_enabled = 0/1 '0': don't start gdb server '1': start gdb server at port 'server_port' server_port = TCP/IP port to start gdb server on valid only if gdb_enabled is set vapi_id = Used to create "fake" vapi log file containing the JTAG proxy messages. */ section debug enabled = 1 gdb_enabled = 1 server_port = 51000 end /* MC SECTION This section configures the memory controller enabled = 0/1 '0': disable memory controller '1': enable memory controller baseaddr = address of first MC register POC = Power On Configuration register index = Index of this memory controller amongst all the memory controllers */ section mc enabled = 1 baseaddr = 0x93000000 POC = 0x0000000a /* 32 bit SSRAM */ index = 0 end /* UART SECTION This section configures the UARTs enabled = <0|1> Enable/disable the peripheral. By default if it is enabled. baseaddr = address of first UART register for this device channel = : The channel parameter indicates the source of received UART characters and the sink for transmitted UART characters. The can be either "file", "xterm", "tcp", "fd", or "tty" (without quotes). A) To send/receive characters from a pair of files, use a file channel: channel=file:, B) To create an interactive terminal window, use an xterm channel: channel=xterm:[]* C) To create a bidirectional tcp socket which one could, for example, access via telnet, use a tcp channel: channel=tcp: D) To cause the UART to read/write from existing numeric file descriptors, use an fd channel: channel=fd:, E) To connect the UART to a physical serial port, create a tty channel: channel=tty:device=/dev/ttyS0,baud=9600 irq = irq number for this device 16550 = 0/1 '0': this device is a UART16450 '1': this device is a UART16550 jitter = in msecs... time to block, -1 to disable it vapi_id = VAPI id of this instance */ section uart enabled = 1 baseaddr = 0x90000000 irq = 2 channel = "file:uart0.rx,uart0.tx" jitter = -1 /* async behaviour */ 16550 = 1 end /* DMA SECTION This section configures the DMAs enabled = <0|1> Enable/disable the peripheral. By default if it is enabled. baseaddr = address of first DMA register for this device irq = irq number for this device vapi_id = VAPI id of this instance */ section dma enabled = 0 baseaddr = 0x9a000000 irq = 11 end /* ETHERNET SECTION This section configures the ETHERNETs enabled = <0|1> Enable/disable the peripheral. By default if it is enabled. baseaddr = address of first ethernet register for this device dma = which controller is this ethernet "connected" to irq = ethernet mac IRQ level rtx_type = use 0 - file interface, 1 - socket interface. Note the socket interface must be configured at build time. rx_channel = DMA channel used for RX tx_channel = DMA channel used for TX rxfile = "" filename, where to read data from txfile = "" filename, where to write data to sockif = "" interface name of ethernet socket vapi_id = VAPI id of this instance */ section ethernet enabled = 0 baseaddr = 0x92000000 irq = 4 rtx_type = 0 rxfile = "eth0.rx" txfile = "eth0.tx" sockif = "eth0" end /* GPIO SECTION This section configures the GPIOs enabled = <0|1> Enable/disable the peripheral. By default if it is enabled. baseaddr = address of first GPIO register for this device irq = irq number for this device base_vapi_id = first VAPI id of this instance GPIO uses 8 consecutive VAPI IDs */ section gpio enabled = 0 baseaddr = 0x91000000 irq = 3 base_vapi_id = 0x0200 end /* VGA SECTION This section configures the VGA/LCD controller enabled = <0|1> Enable/disable the peripheral. By default if it is enabled. baseaddr = address of first VGA register irq = irq number for this device refresh_rate = number of cycles between screen dumps filename = "" template name for generated names (e.g. "primary" produces "primary0023.bmp") */ section vga enabled = 0 baseaddr = 0x97100000 irq = 8 refresh_rate = 100000 filename = "primary" end /* FB SECTION This section configures the frame buffer enabled = <0|1> Enable/disable the peripheral. By default if it is enabled. baseaddr = base address of frame buffer refresh_rate = number of cycles between screen dumps filename = "" template name for generated names (e.g. "primary" produces "primary0023.bmp") */ section fb enabled = 0 baseaddr = 0x97000000 refresh_rate = 1000000 filename = "primary" end /* KBD SECTION This section configures the PS/2 compatible keyboard enabled = <0|1> Enable/disable the peripheral. By default if it is enabled. baseaddr = base address of the keyboard device irq = irq number for this device rxfile = "" filename, where to read data from */ section kbd enabled = 0 baseaddr = 0x94000000 irq = 5 rxfile = "kbd.rx" end /* ATA SECTION This section configures the ATA/ATAPI host controller enabled = <0|1> Enable/disable the peripheral. By default it is enabled. baseaddr = address of first ATA register irq = irq number for this device dev_id = 1/2/3 Which OCIDEC version to imitate rev = Revision of OCIDEC pio_mode0_t1 = <0-255> PIO T1 reset value pio_mode0_t2 = <0-255> PIO T2 reset value pio_mode0_t4 = <0-255> PIO T4 reset value pio_mode0_teoc = <0-255> PIO Teoc reset value dma_mode0_tm = <0-255> DMA Tm reset value dma_mode0_td = <0-255> DMA Td reset value dma_mode0_teoc = <0-255> DMA Teoc reset value Device specific type = ata device 0 type 0: NO_CONNECT: none (not connected) 1: FILE : simulated harddisk 2: LOCAL : local system harddisk file = "" filename for simulated ATA device valid only if dev_type0 == 1 size = size of simulated hard-disk (in MBytes) valid only if dev_type0 == 1 packet = 0: simulated ATA device does NOT implement PACKET command feature set 1: simulated ATA device does implement PACKET command feature set firmware = Firmware to report in `Identify device command' heads = Number of default heads (-1) sectors = Number of default sectors per track mwdma = The highest multiword DMA mode; 2, 1, 0, -1 (No DMA) pio = The highest supported pio mode; 4, 3, 2, 1, 0 FIXME: irq number */ section ata enabled = 0 baseaddr = 0x9e000000 irq = 15 dev_id = 1 rev = 0 pio_mode0_t1 = 6 pio_mode0_t2 = 28 pio_mode0_t4 = 2 pio_mode0_teoc = 23 dma_mode0_tm = 4 dma_mode0_td = 21 dma_mode0_teoc = 21 device 0 type = 1 file = "/tmp/sim_atadev0" size = 1 packet = 0 heads = 7 sectors = 32 firmware = "02207031" mwdma = 2 pio = 4 enddevice device 1 type = 0 file = "" size = 0 packet = 0 enddevice end /* CUC SECTION This section configures the OpenRISC Custom Unit Compiler memory_order = none/weak/strong/exact none different memory ordering, even if there are dependencies, burst can be made, width can change weak different memory ordering, if there cannot be dependencies burst can be made, width can change strong same memory ordering, burst can be made, width can change exact exacltly the same memory ordering and widths calling_convention = 0/1 whether programs follow OpenRISC calling conventions enable_bursts = 0/1 whether burst are detected no_multicycle = 0/1 if selected no multicycle logic paths will be generated timings_fn = "" */ section cuc memory_order = weak calling_convention = 1 enable_bursts = 1 no_multicycle = 1 timings_fn = "virtex.tim" end @