head	1.14;
access;
symbols
	V3_0:1.8
	V2_1:1.7;
locks; strict;
comment	@;; @;


1.14
date	2007.06.15.05.46.18;	author rhoads;	state Exp;
branches;
next	1.13;
commitid	524c467227a54567;

1.13
date	2007.05.19.23.40.41;	author rhoads;	state Exp;
branches;
next	1.12;
commitid	630c464f8af64567;

1.12
date	2007.03.28.05.37.33;	author rhoads;	state Exp;
branches;
next	1.11;
commitid	26ad4609ff1a4567;

1.11
date	2007.02.14.19.00.06;	author rhoads;	state Exp;
branches;
next	1.10;
commitid	5f0145d35c344567;

1.10
date	2006.10.05.05.24.09;	author rhoads;	state Exp;
branches;
next	1.9;
commitid	7c87452496f74567;

1.9
date	2006.03.17.03.08.51;	author rhoads;	state Exp;
branches;
next	1.8;
commitid	7b3441a283f4567;

1.8
date	2004.11.11.03.20.21;	author rhoads;	state Exp;
branches;
next	1.7;

1.7
date	2003.03.11.05.43.17;	author rhoads;	state Exp;
branches;
next	1.6;

1.6
date	2002.05.30.02.05.19;	author rhoads;	state Exp;
branches;
next	1.5;

1.5
date	2002.03.11.02.19.30;	author rhoads;	state Exp;
branches;
next	1.4;

1.4
date	2002.02.06.21.28.45;	author rhoads;	state Exp;
branches;
next	1.3;

1.3
date	2002.01.16.03.11.51;	author rhoads;	state Exp;
branches;
next	1.2;

1.2
date	2002.01.15.04.45.01;	author rhoads;	state Exp;
branches;
next	1.1;

1.1
date	2002.01.13.03.39.37;	author rhoads;	state Exp;
branches;
next	;


desc
@@


1.14
log
@Defined InitStack
@
text
@##################################################################
# TITLE: Boot Up Code
# AUTHOR: Steve Rhoads (rhoadss@@yahoo.com)
# DATE CREATED: 1/12/02
# FILENAME: boot.asm
# PROJECT: Plasma CPU core
# COPYRIGHT: Software placed into the public domain by the author.
#    Software 'as is' without warranty.  Author liable for nothing.
# DESCRIPTION:
#    Initializes the stack pointer and jumps to main().
##################################################################
   #Reserve 512 bytes for stack
   .comm InitStack, 512

   .text
   .align 2
   .global entry
   .ent	entry
entry:
   .set noreorder

   #These four instructions should be the first instructions.
   #convert.exe previously initialized $gp, .sbss_start, .bss_end, $sp
   la    $gp, _gp             #initialize global pointer
   la    $5, __bss_start      #$5 = .sbss_start
   la    $4, _end             #$2 = .bss_end
   la    $sp, InitStack+488   #initialize stack pointer

$BSS_CLEAR:
   sw    $0, 0($5)
   slt   $3, $5, $4
   bnez  $3, $BSS_CLEAR
   addiu $5, $5, 4

   jal   main
   nop
$L1:
   j $L1

   .end entry


###################################################
   #address 0x3c
   .global interrupt_service_routine
   .ent interrupt_service_routine
interrupt_service_routine:
   .set noreorder
   .set noat

   #Registers $26 and $27 are reserved for the OS
   #Save all temporary registers
   #Slots 0($29) through 12($29) reserved for saving a0-a3
   addi  $29, $29, -104  #adjust sp
   sw    $1,  16($29)    #at
   sw    $2,  20($29)    #v0
   sw    $3,  24($29)    #v1
   sw    $4,  28($29)    #a0
   sw    $5,  32($29)    #a1
   sw    $6,  36($29)    #a2
   sw    $7,  40($29)    #a3
   sw    $8,  44($29)    #t0
   sw    $9,  48($29)    #t1
   sw    $10, 52($29)    #t2
   sw    $11, 56($29)    #t3
   sw    $12, 60($29)    #t4
   sw    $13, 64($29)    #t5
   sw    $14, 68($29)    #t6
   sw    $15, 72($29)    #t7
   sw    $24, 76($29)    #t8
   sw    $25, 80($29)    #t9
   sw    $31, 84($29)    #lr
   mfc0  $26, $14        #C0_EPC=14 (Exception PC)
   addi  $26, $26, -4    #Backup one opcode
   sw    $26, 88($29)    #pc
   mfhi  $27
   sw    $27, 92($29)    #hi
   mflo  $27
   sw    $27, 96($29)    #lo

   lui   $6,  0x2000    
   lw    $4,  0x20($6)   #IRQ_STATUS
   lw    $6,  0x10($6)   #IRQ_MASK
   and   $4,  $4, $6
   jal   OS_InterruptServiceRoutine
   addi  $5,  $29, 0

   #Restore all temporary registers
   lw    $1,  16($29)    #at
   lw    $2,  20($29)    #v0
   lw    $3,  24($29)    #v1
   lw    $4,  28($29)    #a0
   lw    $5,  32($29)    #a1
   lw    $6,  36($29)    #a2
   lw    $7,  40($29)    #a3
   lw    $8,  44($29)    #t0
   lw    $9,  48($29)    #t1
   lw    $10, 52($29)    #t2
   lw    $11, 56($29)    #t3
   lw    $12, 60($29)    #t4
   lw    $13, 64($29)    #t5
   lw    $14, 68($29)    #t6
   lw    $15, 72($29)    #t7
   lw    $24, 76($29)    #t8
   lw    $25, 80($29)    #t9
   lw    $31, 84($29)    #lr
   lw    $26, 88($29)    #pc
   lw    $27, 92($29)    #hi
   mthi  $27
   lw    $27, 96($29)    #lo
   mtlo  $27
   addi  $29, $29, 104   #adjust sp

isr_return:
   ori   $27, $0, 0x1    #re-enable interrupts
   jr    $26
   mtc0  $27, $12        #STATUS=1; enable interrupts

   .end interrupt_service_routine
   .set at


###################################################
   .global OS_AsmInterruptEnable
   .ent OS_AsmInterruptEnable
OS_AsmInterruptEnable:
   .set noreorder
   mfc0  $2, $12
   jr    $31
   mtc0  $4, $12            #STATUS=1; enable interrupts
   #nop
   .set reorder
   .end OS_AsmInterruptEnable


###################################################
   .global  OS_AsmInterruptInit
   .ent    OS_AsmInterruptInit
OS_AsmInterruptInit:
   .set noreorder
   #Patch interrupt vector to 0x1000003c
   la    $5, OS_AsmPatchValue
   lw    $6, 0($5)
   sw    $6, 0x3c($0)
   lw    $6, 4($5)
   sw    $6, 0x40($0)
   lw    $6, 8($5)
   sw    $6, 0x44($0)
   lw    $6, 12($5)
   jr    $31
   sw    $6, 0x48($0)

OS_AsmPatchValue:
   #Registers $26 and $27 are reserved for the OS
   #Code to place at address 0x3c
   lui   $26, 0x1000
   ori   $26, $26, 0x3c
   jr    $26
   nop

   .set reorder
   .end OS_AsmInterruptInit


###################################################
   .global   setjmp
   .ent     setjmp
setjmp:
   .set noreorder
   sw    $16, 0($4)   #s0
   sw    $17, 4($4)   #s1
   sw    $18, 8($4)   #s2
   sw    $19, 12($4)  #s3
   sw    $20, 16($4)  #s4
   sw    $21, 20($4)  #s5
   sw    $22, 24($4)  #s6
   sw    $23, 28($4)  #s7
   sw    $30, 32($4)  #s8
   sw    $28, 36($4)  #gp
   sw    $29, 40($4)  #sp
   sw    $31, 44($4)  #lr
   jr    $31
   ori   $2,  $0, 0

   .set reorder
   .end setjmp


###################################################
   .global   longjmp
   .ent     longjmp
longjmp:
   .set noreorder
   lw    $16, 0($4)   #s0
   lw    $17, 4($4)   #s1
   lw    $18, 8($4)   #s2
   lw    $19, 12($4)  #s3
   lw    $20, 16($4)  #s4
   lw    $21, 20($4)  #s5
   lw    $22, 24($4)  #s6
   lw    $23, 28($4)  #s7
   lw    $30, 32($4)  #s8
   lw    $28, 36($4)  #gp
   lw    $29, 40($4)  #sp
   lw    $31, 44($4)  #lr
   jr    $31
   ori   $2,  $5, 0

   .set reorder
   .end longjmp


###################################################
   .global   OS_AsmMult
   .ent     OS_AsmMult
OS_AsmMult:
   .set noreorder
   multu $4, $5
   mflo  $2
   mfhi  $4
   jr    $31
   sw    $4, 0($6)

   .set reorder
   .end OS_AsmMult


###################################################
   .global OS_Syscall
   .ent OS_Syscall
OS_Syscall:
   .set noreorder
   syscall 0
   jr    $31
   nop
   .set reorder
   .end OS_Syscall


@


1.13
log
@Pass .bss_end to main()
@
text
@d10 1
a10 1
#    Initializes the stack pointer and jumps to main2().
d12 7
a18 4
	.text
	.align	2
	.globl	entry
	.ent	entry
d22 1
a22 1
   #These eight instructions should be the first instructions.
d24 3
a26 3
   la    $gp, _gp             #initialize stack pointer
   la    $4, __bss_start      #$4 = .sbss_start
   la    $2, _end             #$2 = .bss_end
d30 2
a31 2
   sw    $0, 0($4)
   slt   $3, $4, $2
d33 1
a33 1
   addiu $4, $4, 4
d45 2
a46 2
	.globl interrupt_service_routine
	.ent	 interrupt_service_routine
d124 1
a124 1
   .globl OS_AsmInterruptEnable
d137 2
a138 2
	.globl	OS_AsmInterruptInit
   .ent     OS_AsmInterruptInit
d166 1
a166 1
	.globl	setjmp
d190 1
a190 1
	.globl	longjmp
d214 1
a214 1
	.globl	OS_AsmMult
d229 1
a229 1
   .globl OS_Syscall
@


1.12
log
@Use linker values _gp, __bss_start, _end, and InitStack
@
text
@d23 1
a23 1
   la    $5, _end             #$5 = .bss_end
d28 1
a28 1
   slt   $3, $4, $5
@


1.11
log
@Implemented BREAK and SYSCALL opcodes
@
text
@d19 6
a24 10
   #These eight instructions must be the first instructions.
   #convert.exe will correctly initialize $gp, .sbss_start, .bss_end, $sp
   lui   $gp, 0
   ori   $gp, $gp, 0          #initialize $gp
   lui   $4, 0
   ori   $4, $4, 0            #$4 = .sbss_start
   lui   $5, 0
   ori   $5, $5, 0            #$5 = .bss_end
   lui   $sp, 0
   ori   $sp, $sp, 0xfff0     #initialize stack pointer
d50 1
@


1.10
log
@Pass stack pointer to ISR
@
text
@a80 1
   addi  $5,  $29, 0
d84 1
d86 1
a86 1
   and   $4, $4, $6
d114 1
d226 14
@


1.9
log
@Support Plasma version 3 and the Plasma RTOS
@
text
@d81 4
a84 3
   lui   $5,  0x2000    
   lw    $4,  0x20($5)   #IRQ_STATUS
   lw    $6,  0x10($5)   #IRQ_MASK
@


1.8
log
@Added better spacing
@
text
@d20 1
a20 1
   #convert.exe will correctly initialize $gp
d22 1
a22 2
   ori   $gp, $gp, 0
   #convert.exe will set $4=.sbss_start $5=.bss_end
d24 1
a24 1
   ori   $4, $4, 0
d26 1
a26 1
   ori   $5, $5, 0
d29 1
d36 1
a36 1
   jal   main2
d41 4
d46 2
d49 70
a118 14
   #registers $26 and $27 are reserved for the OS
   ori   $26, $0, 0xffff
   ori   $27, $0, 46
   sb    $27, 0($26)         #echo out '.'
   
   #normally clear the interrupt source here

   #return and re-enable interrupts
   ori   $26, $0, 0x1
   mfc0  $27, $14      #C0_EPC=14
   jr    $27
   mtc0  $26, $12      #STATUS=1; enable interrupts
   .set reorder
   .end	entry
d122 3
a124 3
   .globl isr_enable
   .ent isr_enable
isr_enable:
d126 1
d129 1
d131 1
a131 1
   .end isr_enable
d135 3
a137 3
	.globl	putchar
	.ent	putchar
putchar:
d139 11
a149 1
   li    $5, 0xffff
d151 10
a160 4
   #Uncomment to make each character on a seperate line
   #The VHDL simulator buffers the lines
#   sb   $4, 0($5)
#   ori  $4, $0, '\n'
d162 18
d181 2
a182 1
   sb    $4, 0($5)
d184 1
a184 1
   .end putchar
d188 16
a203 12
	.globl	puts
	.ent	puts
puts:
   .set noreorder
   ori   $5,$0,0xffff
PUTS1:
   lb    $6, 0($4)
   beqz  $6, PUTS2
   addiu $4, $4, 1
   b     PUTS1
   sb    $6, 0($5)
PUTS2:
d205 2
a206 1
   ori   $2, $0, 0
d208 1
a208 1
   .end puts
d211 13
@


1.7
log
@support > 64kb memory with bss_start, bss_end, sp
@
text
@d21 2
a22 2
   lui   $gp,0
   ori   $gp,$gp,0
d24 6
a29 6
   lui   $4,0
   ori   $4,$4,0
   lui   $5,0
   ori   $5,$5,0
   lui   $sp,0
   ori   $sp,$sp,0xfff0     #initialize stack pointer
d31 4
a34 4
   sw    $0,0($4)
   slt   $3,$4,$5
   bnez  $3,$BSS_CLEAR
   addiu $4,$4,4
d44 3
a46 3
   ori $26,$0,0xffff
   ori $27,$0,46
   sb $27,0($26)           #echo out '.'
d51 4
a54 4
   ori $26,$0,0x1
   mfc0 $27,$14      #C0_EPC=14
   jr $27
   mtc0 $26,$12      #STATUS=1; enable interrupts
d56 1
a56 1
	.end	entry
d64 2
a65 2
   jr $31
   mtc0  $4,$12            #STATUS=1; enable interrupts
d75 1
a75 1
   li $5,0xffff
d79 2
a80 2
#   sb $4,0($5)
#   ori $4,$0,'\n'
d82 2
a83 2
   jr $31
   sb $4,0($5)
d93 1
a93 1
   ori $5,$0,0xffff
d95 5
a99 5
   lb $6,0($4)
   beqz $6,PUTS2
   addiu $4,$4,1
   b PUTS1
   sb $6,0($5)
d101 2
a102 2
   jr $31
   ori $2,$0,0
@


1.6
log
@Altera
@
text
@d19 1
a19 1
   #These nine instructions must be the first instructions
d24 6
a29 3
   ori   $4,$0,0
   ori   $5,$0,0
   ori   $sp,$0,0xfff0     #initialize stack pointer
d41 1
a41 1
   #address 0x30
@


1.5
log
@Renamed M-lite to Plasma
@
text
@d19 1
a19 1
   #These eight instructions must be the first instructions
d26 1
d33 1
a33 2
   ori   $sp,$0,0xfff0     #initialize stack pointer
	jal	main2
@


1.4
log
@Changed name to M-lite to avoid trademark issues.
@
text
@d6 1
a6 1
# PROJECT: M-lite CPU core
@


1.3
log
@added puts()
@
text
@d6 1
a6 1
# PROJECT: MIPS CPU core
@


1.2
log
@setup $gp and zero .sbss and .bss
@
text
@d74 2
a75 1
   #uncomment to make each character on a seperate line
d83 19
@


1.1
log
@Startup code.
@
text
@d19 14
a32 3
   ori   $sp,$0,0x8000     #initialize stack pointer
   ori   $4,$0,1
   mtc0  $4,$12            #STATUS=1; enable interrupts
a36 8
   nop
   nop

isr_storage:        #address 0x20
   nop
   nop
   nop
   nop
d40 4
a43 7
   sw $4,-4($sp)

   sw $5,-8($sp)
   ori $5,$0,0xffff
   ori $4,$0,46
   sb $4,0($5)      #echo out '.'
   lw $5,-8($sp)
a45 9
   #re-enable interrupts
   ori $4,$0,0x1
   mtc0 $4,$12      #STATUS=1; enable interrupts

   #FIXME there is a small race condition here!

   mfc0 $4,$14      #C0_EPC=14
   j $4
   lw $4,-4($sp)
d47 5
d54 29
@