head 1.1; branch 1.1.1; access ; symbols MD5:1.1.1.1 INITIAL:1.1.1; locks ; strict; comment @# @; 1.1 date 2005.06.13.01.47.41; author verilogcores; state Exp; branches 1.1.1.1; next ; commitid b6342ace5bb4567; 1.1.1.1 date 2005.06.13.01.47.41; author verilogcores; state Exp; branches ; next ; commitid b6342ace5bb4567; desc @@ 1.1 log @Initial revision @ text @/******************************************************* * 32 bit Adder * *******************************************************/ module add32 ( In0, In1, Out ); input [31:0] In0; input [31:0] In1; output [31:0] Out; wire [31:0] Out; assign Out[31:0] = In0 + In1; endmodule @ 1.1.1.1 log @initial @ text @@