head 1.1; access; symbols; locks; strict; comment @# @; 1.1 date 2008.07.03.16.53.44; author dimo; state Exp; branches; next ; commitid 1ed4486d04104567; desc @@ 1.1 log @*** empty log message *** @ text @;Laufschrift fuer FPGA-Prozessor ;Anzeige von "VHDL" ;Richtungsumschaltungueber Tastatur ;Andre Lange ;18.9.96 ; Initialisierung lda #32 ;Space sta anz3 sta anz2 sta anz1 sta anz0 lda #86 ;V sta buf3 lda #72 ;H sta buf2 lda #68 ;D sta buf1 lda #76 ;L sta buf0 begin lda #1 ;Warteschleife was 128 sta 0 lda #1 ;was 255 sta 1 wait lda 1 ldb #1 ;was 255 add sta 1 jmpc wait lda 0 ldb #1 ;was 255 add sta 0 jmpc wait lda 251 ;Tastaturabfrage jmpz back lda anz3 sta zbuf lda anz2 sta anz3 lda anz1 sta anz2 lda anz0 sta anz1 lda buf3 sta anz0 lda buf2 sta buf3 lda buf1 sta buf2 lda buf0 sta buf1 lda zbuf sta buf0 jmp begin back lda buf0 sta zbuf lda buf1 sta buf0 lda buf2 sta buf1 lda buf3 sta buf2 lda anz0 sta buf3 lda anz1 sta anz0 lda anz2 sta anz1 lda anz3 sta anz2 lda zbuf sta anz3 jmp begin ;Deklaration der Variablen buf0 db 0 buf1 db 0 buf2 db 0 buf3 db 0 zbuf db 0 .mem 252 anz0 db 0 anz1 db 0 anz2 db 0 anz3 db 0 @