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OPENCORES
project: 5x5Gbps CRC Generator designed with Standard Cells
Project: 5x4Gbps CRC Generator designed with Standard Cells
Details
Category: High-Speed Wireline Communications
Last updated: 28/5/2001
Created: 28/5/2001
Stage: Production/Stable
Description
A 32-bit parallel and highly pipelined Cyclic Redundancy Code (CRC) generator is presented. The design can handle 5 different channels at an input rate of 2Gbps each (the total output throughput is 5x4Gbps.)
The generated CRCs are compatible with the 32-bit Ethernet standards. The circuit has been implemented with standard cells in a 0.35Micron standard CMOS process using the properties of Galois Fields and has been conceived as a "free" IP.
Status
Downloads
| Date |
Description |
Link |
| 15/12/2001 |
The paper presented at the IEEE Student Paper Contest in Cairo, Egypt. It shows the main highlights of the design and the algorithm.
|
CRC_ie3_contest.pdf |
| 28/5/2001 |
Complete project (documentation, code, testbench).
|
CRC-generator.tgz |
| 10/6/2002 |
README file.
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README |
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