head	1.5;
access;
symbols
	dirac_0_0_1_0:1.1.1.1 dirac:1.1.1;
locks; strict;
comment	@# @;


1.5
date	2006.09.06.18.41.06;	author petebleackley;	state Exp;
branches;
next	1.4;
commitid	15ee44ff163a4567;

1.4
date	2006.08.18.14.29.35;	author petebleackley;	state Exp;
branches;
next	1.3;
commitid	7bb044e5ceb74567;

1.3
date	2005.05.27.16.00.30;	author petebleackley;	state Exp;
branches;
next	1.2;
commitid	7ad1429742e04567;

1.2
date	2005.04.26.13.40.14;	author petebleackley;	state Exp;
branches;
next	1.1;
commitid	13af426e42d94567;

1.1
date	2005.03.30.10.09.49;	author petebleackley;	state Exp;
branches
	1.1.1.1;
next	;

1.1.1.1
date	2005.03.30.10.09.49;	author petebleackley;	state Exp;
branches;
next	;


desc
@@


1.5
log
@Adaptive probability models now implemented in the decoder. Testbench for decoding added. Synthesis reports added to documentation section
@
text
@-- ***** BEGIN LICENSE BLOCK *****
-- 
-- $Id: ArithmeticCoderTestbench.vhd,v 1.3 2005/05/27 16:00:28 petebleackley Exp $ $Name:  $
-- *
-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
-- *
-- * The contents of this file are subject to the Mozilla Public License
-- * Version 1.1 (the "License"); you may not use this file except in compliance
-- * with the License. You may obtain a copy of the License at
-- * http://www.mozilla.org/MPL/
-- *
-- * Software distributed under the License is distributed on an "AS IS" basis,
-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
-- * the specific language governing rights and limitations under the License.
-- *
-- * The Original Code is BBC Research and Development code.
-- *
-- * The Initial Developer of the Original Code is the British Broadcasting
-- * Corporation.
-- * Portions created by the Initial Developer are Copyright (C) 2004.
-- * All Rights Reserved.
-- *
-- * Contributor(s): Peter Bleackley (Original author)
-- *
-- * Alternatively, the contents of this file may be used under the terms of
-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
-- * the GPL or the LGPL are applicable instead of those above. If you wish to
-- * allow use of your version of this file only under the terms of the either
-- * the GPL or LGPL and not to allow others to use your version of this file
-- * under the MPL, indicate your decision by deleting the provisions above
-- * and replace them with the notice and other provisions required by the GPL
-- * or LGPL. If you do not delete the provisions above, a recipient may use
-- * your version of this file under the terms of any one of the MPL, the GPL
-- * or the LGPL.
-- * ***** END LICENSE BLOCK ***** */

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
use IEEE.std_logic_textio.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use STD.textio.all;

ENTITY arithmeticcoder_ArithmeticCoderTestbench_vhd_tb IS
END arithmeticcoder_ArithmeticCoderTestbench_vhd_tb;

ARCHITECTURE behavior OF arithmeticcoder_ArithmeticCoderTestbench_vhd_tb IS 

	COMPONENT arithmeticcoder
	PORT(
		ENABLE : IN std_logic;
		DATA_IN : IN std_logic;
		CONTEXT_ENABLE : in std_logic;
		CONTEXT_IN : in std_logic_vector (5 downto 0);
		HALVECOUNTS_IN : in std_logic;
		FLUSH : in std_logic;
		RESET : IN std_logic;
		CLOCK : IN std_logic;          
		SENDING : OUT std_logic;
		DATA_OUT : OUT std_logic;
		FLUSH_COMPLETE : out std_logic
		);
	END COMPONENT;
	component EXP_GOLOMB_COUNTER
	port( DATA_IN : in std_logic_vector (31 downto 0);
		TEST : in std_logic;
		RESET : in std_logic;
		CLOCK : in std_logic;
		COUNTING : out std_logic;
		DATA_OUT : out std_logic);
	end component EXP_GOLOMB_COUNTER;

	SIGNAL ENABLE :  std_logic;
	SIGNAL DATA_IN :  std_logic := '0';
	SIGNAL RESET :  std_logic := '1';
	SIGNAL CLOCK :  std_logic := '0';
	signal FLUSH : std_logic := '0';
	signal HALVECOUNTS : std_logic := '0';
	SIGNAL SENDING :  std_logic;
	SIGNAL DATA_OUT :  std_logic;
	signal TRANSMIT :	std_logic;
	signal DATA_TRANSFER :	std_logic;
	signal FLUSH_COMPLETE : std_logic;
	signal DATA_IN2 :	std_logic_vector (0 downto 0);
	signal BUFFERED2 : std_logic_vector (0 downto 0);
	signal FIFO_EMPTY : std_logic;
	signal BUFFERED : std_logic;
	constant PERIOD : time := 16 ns;
	signal CONTEXT_ENABLE : std_logic;
	signal DECODER_CONTEXT_ENABLE : std_logic;
	signal NUMBITS : std_logic_vector (31 downto 0) := "00000000000000000000000000000000";
	signal NEXTNUMBITS : std_logic_vector (31 downto 0);
	signal NUMBYTES : std_logic_vector (28 downto 0);
	signal CONTEXT_IN : std_logic_vector (5 downto 0) := "000000";
	signal DECODER_CONTEXT : std_logic_vector (5 downto 0) := "000000";
	signal BYTECOUNT : std_logic_vector (31 downto 0);
	signal EXP_GOLOMB_READY : std_logic;
	signal EXP_GOLOMB_DATA : std_logic;
	signal BYTE_INSERT : std_logic := '0';
	signal COMPVAL : character;
	signal SUPPRESS_READ : std_logic := '0';
	type ENCODER_STATUS is (INIT, INIT2, HEADERS, CODING, FLUSHING, EXP_GOLOMB, WRITE_DATA, FINISHED);
	signal STATE : ENCODER_STATUS := INIT;
	type RAM is array (65535 downto 0) of integer;
	signal STORAGE : RAM;
	type CHARFILE is file of character;
	file raw_data : CHARFILE open read_mode is "test1.dr0";
	file contexts : CHARFILE open read_mode is "test1.ctx";
	file coded_stream : CHARFILE open write_mode is "test1.drc";
	file comparison_data : CHARFILE open read_mode is "test1.dr1";
	type INTARRAY is array (7 downto 0) of integer;
	function CONTEXT_INTERPRET(CONTEXT : integer) return std_logic_vector is
	variable VALUE : std_logic_vector(5 downto 0);
	begin
		if CONTEXT >= 128 then
			VALUE(5) := '1';
		else
			VALUE(5) := '0';
		end if;
		if (CONTEXT mod 128) >= 64 then
			VALUE(4) := '1';
		else
			VALUE(4) := '0';
		end if;
		if (CONTEXT mod 64) >= 32 then
			VALUE(3) := '1';
		else
			VALUE(3) := '0';
		end if;
		if (CONTEXT mod 32) >= 16 then
			VALUE(2) := '1';
		else
			VALUE(2) := '0';
		end if;
		if (CONTEXT mod 16) >= 8 then
			VALUE(1) := '1';
		else
			VALUE(1) := '0';
		end if;
		if (CONTEXT mod 8) >= 4 then
			VALUE(0) := '1';
		else
			VALUE(0) := '0';
		end if;
		return VALUE;
	end function CONTEXT_INTERPRET;
BEGIN

	uut: arithmeticcoder 
	PORT MAP(
		ENABLE => ENABLE,
		DATA_IN => DATA_IN,
		CONTEXT_ENABLE => CONTEXT_ENABLE,
		CONTEXT_IN => CONTEXT_IN,
		HALVECOUNTS_IN => HALVECOUNTS,
		FLUSH => FLUSH,
		RESET => RESET,
		CLOCK => CLOCK,
		SENDING => TRANSMIT,
		DATA_OUT => DATA_TRANSFER,
		FLUSH_COMPLETE => FLUSH_COMPLETE
	);
	
	EGC: EXP_GOLOMB_COUNTER
	port map(
		DATA_IN => BYTECOUNT,
		TEST => FLUSH_COMPLETE,
		RESET => RESET,
		CLOCK => CLOCK,
		COUNTING => EXP_GOLOMB_READY,
		DATA_OUT => EXP_GOLOMB_DATA);
		
	

	CLOCK <= not CLOCK after PERIOD/2;
	
 --*** Test Bench - User Defined Section ***
   tb : PROCESS (CLOCK)
	variable POSITION : integer;
	variable EGPOSITION : integer;
	variable PLACE : integer;
	variable READVAL : character;
	variable WRITEVAL : integer;
	variable CONTEXT : integer;
	variable DATA : integer;
	variable COMPDATA : integer;
	variable THRESHOLD : integer;
	variable INDEX : integer range 0 to 536870911;
	variable READ_DATA : INTARRAY := (0,0,0,0,0,0,0,0); 
	variable DUMMY : character;
	
   BEGIN
		if CLOCK'event and CLOCK = '1' then
			if STATE = INIT then
				if READ_DATA = ( 16#4B#, 16#57#, 16#2D#, 16#44#, 16#49#, 16#52#, 16#41#, 16#43#) then
					STATE <= INIT2;
					RESET <= '0';
				else
					READ_DATA(7 downto 1) := READ_DATA(6 downto 0);
					read(raw_data,READVAL);
					READ_DATA(0) := character'pos(READVAL);
				end if;
			elsif STATE = INIT2 then
				if READ_DATA (7 downto 3) = ( 16#44#, 16#49#, 16#52#, 16#41#, 16#43#) then
					STATE <= HEADERS;
					WRITEVAL := 0;
					EGPOSITION := 128;
				else
					WRITEVAL := READ_DATA(7);
					write(coded_stream,character'val(WRITEVAL));
					READ_DATA(7 downto 1) := READ_DATA (6 downto 0);
				end if;
			elsif STATE = HEADERS then
				if READ_DATA (7 downto 3) = ( 16#42#, 16#42#, 16#43#, 16#44#, 16#AC# ) then
					STATE <= CODING;
					PLACE := 0;
					POSITION := 0;
					RESET <= '1';
					ENABLE <= '0';
					DATA_IN <= '0';
					CONTEXT_ENABLE <= '0';
					CONTEXT_IN <= "000000";
					HALVECOUNTS <= '0';
					FLUSH <= '0';
					if SUPPRESS_READ = '0' then
						read(comparison_data,DUMMY);
						COMPVAL <= DUMMY;
					end if;
				elsif READ_DATA (7 downto 3) = (16#42#, 16#42#, 16#43#, 16#44#, 16#D0# ) then
					STATE <= FINISHED;
				else
					if EGPOSITION = 128 then
						read(raw_data,READVAL);
						READ_DATA(2) := character'pos(READVAL);
					end if;
					if READ_DATA(7) > 127 then
						WRITEVAL := WRITEVAL + EGPOSITION;
					end if;

					for I in 7 downto 2 loop
						if READ_DATA(I) > 127 then
							READ_DATA(I) := (READ_DATA(I) -128) * 2;
						else
							READ_DATA(I) := READ_DATA(I) * 2;
						end if;
						if READ_DATA(I-1) > 127 then 
							READ_DATA(I) := READ_DATA(I) + 1;
						end if;
					end loop;
					if EGPOSITION = 1 then
						write(coded_stream,character'val(WRITEVAL));
						EGPOSITION := 128;
						WRITEVAL := 0;
					else
						EGPOSITION := EGPOSITION / 2;
					end if;
				end if;
			elsif STATE = CODING then
				if PLACE = 0 then
					RESET <= '0';
				end if;
				if PLACE mod 5 = 0 then
					read(contexts,READVAL);
					CONTEXT := character'pos(READVAL);
					CONTEXT_ENABLE <= '1';
					if CONTEXT mod 2 = 1 then
						CONTEXT_IN <= "000000";
						HALVECOUNTS <= '0';
						STATE <= FLUSHING;
						FLUSH <= '1';
					else 
						CONTEXT_IN <= CONTEXT_INTERPRET(CONTEXT); 
						if (CONTEXT mod 4) > 1 then
							HALVECOUNTS <= '1';
						else
							HALVECOUNTS <= '0';
						end if;
						FLUSH <= '0';
					end if;
				elsif PLACE mod 5 = 3 then
					if POSITION = 0 then
						POSITION := 128;
						READ(raw_data,READVAL);
						DATA := character'pos(READVAL);
					end if;
					if (DATA / POSITION) mod 2 = 1 then
						DATA_IN <= '1';
					else
						DATA_IN <= '0';
					end if;
					ENABLE <= '1';
					POSITION := POSITION / 2;
				else
					CONTEXT_ENABLE <= '0';
					ENABLE <= '0';
				end if;
				PLACE := PLACE + 1;
			elsif STATE = FLUSHING then
				if FLUSH = '1' then
					FLUSH <= '0';
					CONTEXT_ENABLE <= '0';
				end if;
				if FLUSH_COMPLETE = '1' then
					STATE <= EXP_GOLOMB;
					PLACE := 7;
					POSITION := 128;
					READ_DATA(7) := 0;
				end if;
			elsif STATE = EXP_GOLOMB then
				if EXP_GOLOMB_READY = '0' then
					STATE <= WRITE_DATA;
					INDEX := 0;
					if EGPOSITION /= 128 then
						write(coded_stream,character'val(WRITEVAL));
					end if;
					PLACE := 7;
				else
					if EXP_GOLOMB_DATA = '1' then
						WRITEVAL := WRITEVAL + EGPOSITION;
					end if;
					if EGPOSITION = 1 then
						EGPOSITION := 128;
						write(coded_stream,character'val(WRITEVAL));
						WRITEVAL := 0;
					else
						EGPOSITION := EGPOSITION / 2;
					end if;
				end if;
				
			elsif STATE  = WRITE_DATA then
				if INDEX = (conv_integer(NUMBYTES)-1) then
					STATE <= HEADERS;
					WRITEVAL := 0;
				else
					if PLACE < 3 then
						WRITEVAL := READ_DATA(7);
						write(coded_stream,character'val(WRITEVAL));
						READ_DATA (7 downto 3) := READ_DATA (6 downto 2);
						READ_DATA (2) := STORAGE(INDEX);
					else
						READ_DATA (PLACE) := STORAGE(INDEX);
						PLACE := PLACE - 1;
					end if;
					INDEX := INDEX + 1;
				end if;
			else --STATE = FINISHED
				if READ_DATA (7 downto 3) = (0, 0, 0, 0, 0) then
					report ("finished") severity failure;
				else
					WRITEVAL := READ_DATA(7);
					write(coded_stream,character'val(WRITEVAL));
					READ_DATA (7 downto 3) := READ_DATA (6 downto 3) & 0;
				end if;
			end if;
		end if;
			
			

   END PROCESS;


COUNT_BITS: process (CLOCK)
	begin
	if (CLOCK'event and CLOCK='1') then
		if RESET = '1' then
			NUMBITS <= "00000000000000000000000000000000";
		else
			if TRANSMIT = '1' then
				NUMBITS <= NUMBITS + "00000000000000000000000000000001";
			end if;
			if BYTE_INSERT = '1' then
				NUMBITS <= NUMBITS + "00000000000000000000000000001000";
			end if;
		end if;
	end if;
	end process;
	
NEXTNUMBITS <= NUMBITS + "00000000000000000000000000000111";

NUMBYTES <= NEXTNUMBITS (31 downto 3);
	
	BYTECOUNT <=  "0000000000000000" & NUMBYTES(15 downto 0);


WRITE_MEMORY: process(CLOCK)
	variable INCREMENT: integer;
	variable DATA : integer;
	variable COMPARISON : character;
	variable COMPDATA : integer;
	variable COMPDATA2 : integer;
begin
	if CLOCK'event and CLOCK = '1' then
		if RESET = '1' then
			INCREMENT := 128;
			BYTE_INSERT <= '0';
			if SUPPRESS_READ = '0' then
				COMPDATA := character'pos(COMPVAL);
			end if;
			COMPDATA2 := 0;
			DATA := 0;
		elsif TRANSMIT = '1' then
			if (COMPDATA rem (INCREMENT*2)) >= INCREMENT then
				COMPDATA2 := COMPDATA2 + INCREMENT;
			end if;
			if DATA_TRANSFER = '1' then
				DATA := DATA + INCREMENT;
			end if;
			assert COMPDATA2 = DATA report "ENCODER HAS DIVERGED" severity failure;
			if INCREMENT = 1 then
				STORAGE(conv_integer(NUMBYTES)-1) <= DATA;
				DATA := 0;
				INCREMENT := 128;
				read(comparison_data,COMPARISON);
				COMPDATA := character'pos(COMPARISON);
				COMPDATA2 := 0;
				if NUMBYTES >= "00000000000000000000000000100" then
					if STORAGE((conv_integer(NUMBYTES) -4) downto (conv_integer(NUMBYTES) - 1)) = (16#42#, 16#42#, 16#43#, 16#44#) then
						STORAGE(conv_integer(NUMBYTES)) <= 16#FF#;
						BYTE_INSERT <= '1';
					end if;
				end if;
			else
				INCREMENT := INCREMENT/2;
			end if;
		elsif FLUSH_COMPLETE = '1' then
			if INCREMENT /= 128 then 
				STORAGE(conv_integer(NUMBYTES)) <= DATA;
				if NUMBYTES >= "00000000000000000000000000100" then
					if STORAGE((conv_integer(NUMBYTES) -3) downto (conv_integer(NUMBYTES))) = (16#42#, 16#42#, 16#43#, 16#44#) then
						STORAGE(conv_integer(NUMBYTES)+1) <= 16#FF#;
						BYTE_INSERT <= '1';
					end if;
				end if;
				SUPPRESS_READ <= '0';
			else
				SUPPRESS_READ <= '1';
			end if;
		end if;
		if BYTE_INSERT = '1' then
			BYTE_INSERT <= '0';
		end if;
	end if;
end process WRITE_MEMORY;

END;
@


1.4
log
@Complete implementation of adaptive arithmetic coding, suitable for Dirac 0.5.3
@
text
@d3 33
a35 32
-- 
--  Version: MPL 1.1/GPL 2.0/LGPL 2.1
-- 
--  The contents of this file are subject to the Mozilla Public License
--  Version 1.1 (the "License"); you may not use this file except in compliance
--  with the License. You may obtain a copy of the License at
--  http://www.mozilla.org/MPL/
-- 
--  Software distributed under the License is distributed on an "AS IS" basis,
--  WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
--  the specific language governing rights and limitations under the License.
-- 
--  The Original Code is BBC Research and Development code.
-- 
--  The Initial Developer of the Original Code is the British Broadcasting
--  Corporation.
--  Portions created by the Initial Developer are Copyright (C) 2006.
--  All Rights Reserved.
-- 
--  Contributor(s): Peter Bleackley (Original author)
-- 
--  Alternatively, the contents of this file may be used under the terms of
--  the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
--  Public License Version 2.1 (the "LGPL"), in which case the provisions of
--  the GPL or the LGPL are applicable instead of those above. If you wish to
--  allow use of your version of this file only under the terms of the either
--  the GPL or LGPL and not to allow others to use your version of this file
--  under the MPL, indicate your decision by deleting the provisions above
--  and replace them with the notice and other provisions required by the GPL
--  or LGPL. If you do not delete the provisions above, a recipient may use
--  your version of this file under the terms of any one of the MPL, the GPL
--  or the LGPL.
d315 3
a317 1
					write(coded_stream,character'val(WRITEVAL));
@


1.3
log
@Added documentation for fixed-frequency encoding.
Added component CONTEXT_MANAGER to handle conditional probability encoding.
Modified arithmetic coder, arithmetic decoder and testbench for conditional probability encoding.
FIFO now has a RAM based architecture, and it and INPUT_CONTROL are parameterised by width.
All flip-flops are now represented by clocked processes, so the components D_TYPE, ENABLEABLE_D_TYPE, STORE_BLOCK and COUNT_UNIT are no longer necessary.
Added input file "testseq" for testing conditional probability encoding.
@
text
@d3 32
a34 33
-- $Id: ArithmeticCoderTestbench.vhd,v 1.3 2005/05/27 15:35:25 petebleackley Exp $ $Name:  $
-- *
-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
-- *
-- * The contents of this file are subject to the Mozilla Public License
-- * Version 1.1 (the "License"); you may not use this file except in compliance
-- * with the License. You may obtain a copy of the License at
-- * http://www.mozilla.org/MPL/
-- *
-- * Software distributed under the License is distributed on an "AS IS" basis,
-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
-- * the specific language governing rights and limitations under the License.
-- *
-- * The Original Code is BBC Research and Development code.
-- *
-- * The Initial Developer of the Original Code is the British Broadcasting
-- * Corporation.
-- * Portions created by the Initial Developer are Copyright (C) 2004.
-- * All Rights Reserved.
-- *
-- * Contributor(s): Peter Bleackley (Original author)
-- *
-- * Alternatively, the contents of this file may be used under the terms of
-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
-- * the GPL or the LGPL are applicable instead of those above. If you wish to
-- * allow use of your version of this file only under the terms of the either
-- * the GPL or LGPL and not to allow others to use your version of this file
-- * under the MPL, indicate your decision by deleting the provisions above
-- * and replace them with the notice and other provisions required by the GPL
-- * or LGPL. If you do not delete the provisions above, a recipient may use
-- * your version of this file under the terms of any one of the MPL, the GPL
-- * or the LGPL.
a36 9
-- VHDL Test Bench Created from source file arithmeticcoder.vhd -- 13:44:22 01/05/2005
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--
a50 2
--	generic(
--	PROB :	std_logic_vector (9 downto 0));
d56 2
d61 2
a62 1
		DATA_OUT : OUT std_logic
d65 9
a73 21
	component ARITHMETICDECODER
	port (ENABLE : in std_logic;
           DATA_IN : in std_logic;
           NEWCONTEXT :	in std_logic;
           CONTEXT_SELECT : in std_logic_vector (5 downto 0);
           RESET : in std_logic;
           CLOCK : in std_logic;
           SENDING : out std_logic;
           DATA_OUT : out std_logic);
        end component ARITHMETICDECODER;
        component FIFO
        generic (RANK :	integer range 0 to 16;
        	WIDTH : integer range 1 to 16);
        port (	WRITE_ENABLE :	in std_logic;
        	DATA_IN:	in std_logic_vector (WIDTH - 1 downto 0);
        	READ_ENABLE :	in std_logic;
        	RESET :	in std_logic;
        	CLOCK : in std_logic;
       	DATA_OUT :	out std_logic_vector (WIDTH - 1 downto 0);
        	EMPTY :	out std_logic);
        	end component FIFO;
d76 1
a76 1
	SIGNAL RESET :  std_logic;
d78 2
d84 1
a86 1
--	signal FINISHED : std_logic := '0';
d89 1
a89 1
	constant PERIOD : time := 10 ns;
d92 4
a95 1
	signal CONTEXT : std_logic_vector (5 downto 0) := "000000";
d97 51
a147 14
	file TESTDATA :	text open read_mode is "testseq";
	file RESULTS :	text open write_mode is "results";
	type TABLE is array (30 downto 0) of std_logic_vector (5 downto 0);
	constant NCONTEXT0 : TABLE := ("111101","111011","111001","110111",
	"110101","110011","110001","101111","101101","101011","101001",
	"100111","100101","100011","100001","011111","011101","011011",
	"011001","010111","010101","010011","010001","001111","001101",
	"001011","001001","000111","000101","000011","000001");
	constant NCONTEXT1 : TABLE := ("111110","111100","111010","111000",
	"110110","110100","110010","110000","101110","101100","101010",
	"101000","100110","100100","100010","100000","011110","011100",
	"011010","011000","010110","010100","010010","010000","001110",
	"001100","001010","001000","000110","000100","000010");

a150 2
--	generic map(
--	PROB => "1110010000")
d155 3
a157 1
		CONTEXT_IN => CONTEXT,
d161 2
a162 1
		DATA_OUT => DATA_TRANSFER
d164 11
a177 9
	DECODER:	ARITHMETICDECODER
	port map(	ENABLE => TRANSMIT,
	DATA_IN => DATA_TRANSFER,
	NEWCONTEXT => DECODER_CONTEXT_ENABLE,
	CONTEXT_SELECT => DECODER_CONTEXT,
	RESET => RESET,
	CLOCK => CLOCK,
	SENDING => SENDING,
	DATA_OUT => DATA_OUT);
d179 14
a192 3
   tb : PROCESS
	variable GETLINE : line;
	variable INDATA : std_logic;
d194 132
a325 19
		for COUNT in 0 to 5242880 loop
		wait until CLOCK'event and CLOCK = '1';
		if (COUNT < 5242900) then
			if COUNT = 0 then 
				RESET <= '1';
				ENABLE <= '0';
				DATA_IN <= '0';
				CONTEXT_ENABLE <='0';
			elsif COUNT = 1 then
				RESET <= '0';
				CONTEXT_ENABLE <= '1';
			elsif COUNT mod 5 = 0 then
				CONTEXT_ENABLE <= '1';
				ENABLE <= '0';
			elsif	(COUNT - 4) mod 5 = 0 then
			
				if (COUNT - 4)	mod 160 = 0 then
					if not endfile(TESTDATA) then
					readline(TESTDATA,GETLINE);
d328 5
a332 5
				read(GETLINE,INDATA);
				DATA_IN <= INDATA;
				ENABLE <= '1';
				if (CONTEXT > "011110") then
					CONTEXT <= "000000";
d334 5
a338 2
					if (INDATA = '1') then
						CONTEXT <= NCONTEXT1(conv_integer(CONTEXT));
d340 2
a341 1
						CONTEXT <= NCONTEXT0(conv_integer(CONTEXT));
d343 9
a352 3
			else
				ENABLE <= '0';
				CONTEXT_ENABLE <= '0';
d354 4
a357 7
		elsif (COUNT = 5242900) then
			ENABLE <= '1';
			DATA_IN <= '1';
		else
      			wait; -- will wait forever
      		end if;
		end loop;
d360 2
a361 2
	OUTPUT :	process
	variable OUTLINE :	line;
d363 3
a365 5
	for WRITTEN in 0 to 1048576 loop
		wait until CLOCK'event and CLOCK = '1' and SENDING = '1';
		if WRITTEN = 1048576 then
			report "Process Complete" severity failure;
			wait;
d367 5
a371 3
			write(OUTLINE,DATA_OUT);
			if (WRITTEN mod 32) = 31 then
				writeline(RESULTS,OUTLINE);
a372 2

					
d374 1
a374 1
	end loop;
d377 3
a379 10
TESTBUFFER :	FIFO
	generic map(RANK => 11,
	WIDTH => 1)
	port map	(WRITE_ENABLE => ENABLE,
	DATA_IN => DATA_IN2,	
	READ_ENABLE => SENDING,
	RESET => RESET,
	CLOCK => CLOCK,
	DATA_OUT => BUFFERED2,
	EMPTY => FIFO_EMPTY);
d381 1
a381 8
	DATA_IN2(0) <= DATA_IN;
	BUFFERED <= BUFFERED2(0);

FIND_ERROR : postponed process (SENDING, DATA_OUT, BUFFERED)
	begin
	assert (( SENDING /= '1') or (DATA_OUT = BUFFERED))
	report "DIVERGENGE!!!"	severity failure;
	end process FIND_ERROR;		
a382 1
-- *** End Test Bench - User Defined Section ***
d384 7
a390 12
COUNT_BITS: process (CLOCK, TRANSMIT)
	variable BITS_SENT : integer range 0 to 1048576 := 0;
	begin
	if (CLOCK'event and CLOCK='1' and TRANSMIT='1') then
	BITS_SENT := BITS_SENT+1;
	end if;
	end process;


	
CHOOSE_DECODER_CONTEXT:	process(CLOCK)
	begin
d393 41
a433 7
			DECODER_CONTEXT <= "000000";
			DECODER_CONTEXT_ENABLE <= '1';
		elsif SENDING = '1' then
			if DECODER_CONTEXT > "011110" then
				DECODER_CONTEXT <= "000000";
			elsif DATA_OUT = '1' then
				DECODER_CONTEXT <= NCONTEXT1(conv_integer(DECODER_CONTEXT));
d435 1
a435 1
				DECODER_CONTEXT <= NCONTEXT0(conv_integer(DECODER_CONTEXT));
d437 3
a439 3
			DECODER_CONTEXT_ENABLE <= '1';
		else
			DECODER_CONTEXT_ENABLE <= '0';
d442 1
a442 3
end process CHOOSE_DECODER_CONTEXT;


@


1.2
log
@Patch 1
Corrected errors in /src/common/ARITHMETIC_UNIT.vhd and /src/testbench/ArithmeticCoderTestbench.vhd
ARITHMETIC_UNIT.vhd
Corrected width of signal RESULT0 to (16 downto 0)
ArithmeticCoderTestbench.vhd
Removed extraneous inputs CONTEXT_ENABLE and CONTEXT_IN from component specification of ArithmeticCoder
(These belong to a future version)
Specified filename "raw_data" for file input TESTDATA
Added missing end if; in process OUTPUT
@
text
@d1 36
d61 2
a62 2
		generic(
	PROB :	std_logic_vector (9 downto 0));
d66 2
a74 2
	generic(
	PROB :	std_logic_vector (9 downto 0));
d77 2
d84 11
a94 1
 
d103 5
d109 17
a125 2
	file TESTDATA :	text is in "raw_data";
	file RESULTS :	text is out "results";
d130 2
a131 2
	generic map(
	PROB => "1110010000")
d135 2
a145 2
	generic map( 
	PROB => "1110010000")
d148 2
d159 1
a159 1
		for COUNT in 0 to 4194307 loop
d161 16
a176 10
		if COUNT = 0 then 
			RESET <= '1';
			ENABLE <= '0';
			DATA_IN <= '0';
		elsif COUNT = 1 then
			RESET <= '0';

		elsif	(COUNT - 2) mod 4 = 0 then
			if (COUNT < 4194307) then
				if (COUNT - 2)	mod 128 = 0 then
d178 1
d183 9
d193 2
a194 2
				DATA_IN <= '1';
				ENABLE <= '1';
d196 3
a198 3

		elsif COUNT < 4194307 then
			ENABLE <= '0';
d200 2
a201 2
      	wait; -- will wait forever
      	end if;
d218 2
d224 19
d253 26
@


1.1
log
@Initial revision
@
text
@a29 2
		CONTEXT_ENABLE : in std_logic;
		CONTEXT_IN : in std_logic_vector (5 downto 0);
d56 1
a56 3
	signal CONTEXT_ENABLE : std_logic;
	signal CONTEXT : std_logic_vector (5 downto 0) := "000000";
	file TESTDATA :	text is in "";
a66 2
		CONTEXT_ENABLE => CONTEXT_ENABLE,
		CONTEXT_IN => CONTEXT,
d132 1
@


1.1.1.1
log
@Initail commit
@
text
@@