head	1.2;
access;
symbols
	dirac_0_0_1_0:1.1.1.1 dirac:1.1.1;
locks; strict;
comment	@# @;


1.2
date	2005.05.27.16.00.28;	author petebleackley;	state Exp;
branches;
next	1.1;
commitid	7ad1429742e04567;

1.1
date	2005.03.30.10.09.49;	author petebleackley;	state Exp;
branches
	1.1.1.1;
next	;

1.1.1.1
date	2005.03.30.10.09.49;	author petebleackley;	state Exp;
branches;
next	;


desc
@@


1.2
log
@Added documentation for fixed-frequency encoding.
Added component CONTEXT_MANAGER to handle conditional probability encoding.
Modified arithmetic coder, arithmetic decoder and testbench for conditional probability encoding.
FIFO now has a RAM based architecture, and it and INPUT_CONTROL are parameterised by width.
All flip-flops are now represented by clocked processes, so the components D_TYPE, ENABLEABLE_D_TYPE, STORE_BLOCK and COUNT_UNIT are no longer necessary.
Added input file "testseq" for testing conditional probability encoding.
@
text
@-- ***** BEGIN LICENSE BLOCK *****
-- 
-- $Id: FIFO.vhd,v 1.2 2005/05/27 15:35:08 petebleackley Exp $ $Name:  $
-- *
-- * Version: MPL 1.1/GPL 2.0/LGPL 2.1
-- *
-- * The contents of this file are subject to the Mozilla Public License
-- * Version 1.1 (the "License"); you may not use this file except in compliance
-- * with the License. You may obtain a copy of the License at
-- * http://www.mozilla.org/MPL/
-- *
-- * Software distributed under the License is distributed on an "AS IS" basis,
-- * WITHOUT WARRANTY OF ANY KIND, either express or implied. See the License for
-- * the specific language governing rights and limitations under the License.
-- *
-- * The Original Code is BBC Research and Development code.
-- *
-- * The Initial Developer of the Original Code is the British Broadcasting
-- * Corporation.
-- * Portions created by the Initial Developer are Copyright (C) 2004.
-- * All Rights Reserved.
-- *
-- * Contributor(s): Peter Bleackley (Original author)
-- *
-- * Alternatively, the contents of this file may be used under the terms of
-- * the GNU General Public License Version 2 (the "GPL"), or the GNU Lesser
-- * Public License Version 2.1 (the "LGPL"), in which case the provisions of
-- * the GPL or the LGPL are applicable instead of those above. If you wish to
-- * allow use of your version of this file only under the terms of the either
-- * the GPL or LGPL and not to allow others to use your version of this file
-- * under the MPL, indicate your decision by deleting the provisions above
-- * and replace them with the notice and other provisions required by the GPL
-- * or LGPL. If you do not delete the provisions above, a recipient may use
-- * your version of this file under the terms of any one of the MPL, the GPL
-- * or the LGPL.
-- * ***** END LICENSE BLOCK ***** */


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

--  Uncomment the following lines to use the declarations that are
--  provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;

  entity FIFO is
	generic (RANK :	integer range 0 to 16 :=8;
	WIDTH : integer range 1 to 16);
    Port ( WRITE_ENABLE : in std_logic;
           DATA_IN : in std_logic_vector(WIDTH - 1 downto 0);
           READ_ENABLE : in std_logic;
           RESET : in std_logic;
           CLOCK : in std_logic;
           DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0);
           EMPTY : out std_logic);
end FIFO;

architecture RTL of FIFO is


	function TWO_TO_N(N:	integer) return integer is
	variable A:	integer;
	begin
	A := 1;
	for Z in 0 to N - 1 loop
	A := 2*A;
	end loop;
	return A;
	end function TWO_TO_N;
	signal WRITE_ADDRESS :	std_logic_vector (RANK - 1 downto 0);
	signal READ_ADDRESS :	std_logic_vector (RANK - 1 downto 0);
	type MATRIX is
	array (TWO_TO_N(RANK) - 1 downto 0) of std_logic_vector(WIDTH - 1 downto 0);
	signal GET_OUTPUT: MATRIX;

	signal EMPTY_OUT :	std_logic;


begin
-- Counters

COUNT: process (CLOCK)
	begin
	if (CLOCK'event and CLOCK = '1') then
		if (RESET = '1') then
			READ_ADDRESS <= (others => '0');
			WRITE_ADDRESS <= (others => '0');
		else
			if WRITE_ENABLE = '1' then
				WRITE_ADDRESS <= WRITE_ADDRESS + "1";
			end if;
			if READ_ENABLE = '1' and EMPTY_OUT = '0' then
				READ_ADDRESS <= READ_ADDRESS + "1";
			end if;
		end if;	
	end if;
end process COUNT;




ZEROVALUE : process (READ_ADDRESS, WRITE_ADDRESS)
begin
	if READ_ADDRESS = WRITE_ADDRESS then
	EMPTY_OUT <= '1';
	else
	EMPTY_OUT <= '0';
	end if;
end process ZEROVALUE;

EMPTY <= EMPTY_OUT;

SETDATA: process (CLOCK)
	begin
	if CLOCK'event and CLOCK = '1' then
	if WRITE_ENABLE = '1' then
		GET_OUTPUT(conv_integer(WRITE_ADDRESS)) <= DATA_IN;
	end if;
	end if;
	end process SETDATA;


	DATA_OUT <= GET_OUTPUT(conv_integer(READ_ADDRESS));


end RTL;

@


1.1
log
@Initial revision
@
text
@d3 1
a3 1
-- $Id: FIFO.vhd,v 1.0 2005/03/24 10:56:32 petebleackley Exp $ $Name: Dirac_0_0_1 $
d49 3
a51 2
entity FIFO is
	generic (RANK :	integer range 0 to 16 :=8);
d53 1
a53 1
           DATA_IN : in std_logic;
d57 2
a58 2
           DATA_OUT : out std_logic;
			  EMPTY : out std_logic);
d62 2
a63 20
	 component	ENABLEABLE_D_TYPE
	 port (DATA_IN : in std_logic;
	 		ENABLE : in std_logic;
			 CLK : in std_logic;
			 DATA_OUT:	out std_logic);
	end component ENABLEABLE_D_TYPE;
	component D_TYPE
	port(	 D : in std_logic;
           CLOCK : in std_logic;
           Q : out std_logic);
end component D_TYPE;
	component COUNT_UNIT
	port(		INCREMENT : in std_logic;
           DECREMENT : in std_logic;
			  RESET :	in std_logic;
           CLOCK : in std_logic;
           OUTPUT : out std_logic;
           INCREMENT_CARRY : out std_logic;
           DECREMENT_CARRY : out std_logic);
end component COUNT_UNIT;
d73 1
a73 10
	function ZERO_VALUE(ADDRESS:	std_logic_vector) return std_logic is
	begin
	for J in 0 to RANK - 1 loop
	if ADDRESS(J) = '1' then
	return '0';
	end if;
	end loop;
	return '1';
	end function ZERO_VALUE;

a74 2
	signal INC :	std_logic_vector (RANK - 1 downto 0);
	signal DEC : 	std_logic_vector (RANK - 1 downto 0);
d76 1
a76 1
	array (RANK downto 0) of std_logic_vector (TWO_TO_N(RANK) -1 downto 0);
d78 1
a78 7
	signal NEWVAL :	std_logic_vector(TWO_TO_N(RANK) - 1 downto 0);
	signal INCREMENT :	std_logic;
	signal DECREMENT :	std_logic;
	signal TOGGLE :	std_logic;
	signal IS_EMPTY :	std_logic;
	signal ZERO :	std_logic;
	signal NEW_EMPTY : std_logic;
a79 6
	signal NOWRITE :	std_logic;
	signal CHANGED_VALUE : std_logic;
	signal EMPTY_IF_READ :	std_logic;
	signal LOAD_ENABLE : std_logic;
begin
-- Storage registers
d82 2
a83 1
BUILD: for I in 0 to RANK -1 generate
d85 16
a100 22
LSB:	if I = 0 generate
COUNTER : COUNT_UNIT
	port map( INCREMENT => INCREMENT,
				DECREMENT => DECREMENT,
				RESET => RESET,
				CLOCK => CLOCK,
				OUTPUT => READ_ADDRESS(I),
				INCREMENT_CARRY => INC(I),
				DECREMENT_CARRY => DEC(I));

	end generate;

OTHER_BITS:	if I > 0 generate
COUNTER :	COUNT_UNIT
	port map( INCREMENT => INC(I-1),
				DECREMENT => DEC(I-1),
				RESET => RESET,
				CLOCK => CLOCK,
				OUTPUT => READ_ADDRESS(I),
				INCREMENT_CARRY => INC(I),
				DECREMENT_CARRY => DEC(I));
	end generate;
a101 10
MULTIPLEX:	for Z in 0 to TWO_TO_N(I) - 1 generate
OUTPUT_SELECT: process(READ_ADDRESS(RANK - I - 1),GET_OUTPUT(RANK - I -1))
begin
	if READ_ADDRESS(RANK - I - 1) = '1' then
		GET_OUTPUT(RANK - I)(Z) <= GET_OUTPUT(RANK - I - 1)(2*Z + 1);
	else
		GET_OUTPUT(RANK - I)(Z) <= GET_OUTPUT(RANK - I - 1)(2*Z);
	end if;
end process OUTPUT_SELECT;
end generate;
a102 28
STORAGE: if I = RANK - 1 generate
BITS:	for X in 0 to TWO_TO_N(RANK) - 1 generate
STORE:	ENABLEABLE_D_TYPE
			port map (DATA_IN => NEWVAL(X),
			ENABLE => LOAD_ENABLE,
			CLK => CLOCK,
			DATA_OUT => GET_OUTPUT(0)(X));
MOST_RECENT:	if X = 0 generate
	NEWVAL(X) <= DATA_IN and not RESET;
end generate;

OLDER_DATA: if X > 0 generate
	NEWVAL(X) <= GET_OUTPUT(0)(X-1) and not RESET;
end generate;
end generate;
end generate;


end generate;

LOAD_ENABLE <= WRITE_ENABLE or RESET;
INCREMENT <= WRITE_ENABLE and not (READ_ENABLE or EMPTY_OUT);
DECREMENT <= READ_ENABLE and not (WRITE_ENABLE or ZERO);

EMPTY_VALUE:	D_TYPE
	port map(D => IS_EMPTY,
				CLOCK => CLOCK,
				Q => EMPTY_OUT);
a103 1
IS_EMPTY <= NEW_EMPTY or RESET;
d105 1
a105 1
SWITCH_EMPTY: process(TOGGLE,EMPTY_OUT,CHANGED_VALUE)
d107 2
a108 2
	if(TOGGLE = '1') then
		NEW_EMPTY <= CHANGED_VALUE;
d110 1
a110 1
		NEW_EMPTY <= EMPTY_OUT;
d112 1
a112 1
end process SWITCH_EMPTY;
d114 1
a114 4
TOGGLE <= WRITE_ENABLE xor READ_ENABLE;
CHANGED_VALUE <= EMPTY_IF_READ and NOWRITE;
NOWRITE <= not WRITE_ENABLE;
EMPTY_IF_READ <= ZERO or EMPTY_OUT;
d116 8
a124 3
ZERO <= ZERO_VALUE(READ_ADDRESS);

EMPTY <= EMPTY_OUT;
d126 1
a126 1
DATA_OUT <= GET_OUTPUT(RANK)(0);
d129 1
a130 1
end RTL;
@


1.1.1.1
log
@Initail commit
@
text
@@