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1.2
date	2006.10.05.16.17.11;	author petebleackley;	state Exp;
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1.1
date	2006.09.06.18.41.02;	author petebleackley;	state Exp;
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desc
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1.2
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@Restored after CVS server crashed. Changed bitwidths and exp-golomb format to current specification. Placed copy of specification in docs directory
@
text
@Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.36 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.36 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: arithmeticcoder.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "arithmeticcoder.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "arithmeticcoder"
Output Format                      : NGC
Target Device                      : xc2v2000-6-bg575

---- Source Options
Top Module Name                    : arithmeticcoder
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 2
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : arithmeticcoder.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd" in Library work.
Architecture rtl of Entity divider is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/UPDATER.vhd" in Library work.
Architecture rtl of Entity updater is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" in Library work.
Architecture rtl of Entity halving_manager is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/FIFO.vhd" in Library work.
Architecture rtl of Entity fifo is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/INPUT_CONTROL.vhd" in Library work.
Architecture rtl of Entity input_control is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/REGISTER.vhd" in Library work.
Architecture rtl of Entity limit_register is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/ARITHMETIC_UNIT.vhd" in Library work.
Architecture rtl of Entity arithmetic_unit is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/CONVERGENCE_CHECK.vhd" in Library work.
Architecture rtl of Entity convergence_check is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/FOLLOW_COUNTER.vhd" in Library work.
Architecture rtl of Entity follow_counter is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/OUTPUT_UNIT.vhd" in Library work.
Architecture rtl of Entity output_unit is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" in Library work.
Architecture rtl of Entity context_manager is up to date.
Compiling vhdl file "C:/Xilinx/bin/ArithmeticCoder/ARITHMETICCODER.vhd" in Library work.
Architecture rtl of Entity arithmeticcoder is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <arithmeticcoder> (Architecture <rtl>).
Entity <arithmeticcoder> analyzed. Unit <arithmeticcoder> generated.

Analyzing generic Entity <INPUT_CONTROL> (Architecture <rtl>).
	WIDTH = 1
Entity <INPUT_CONTROL> analyzed. Unit <INPUT_CONTROL> generated.

Analyzing generic Entity <FIFO> (Architecture <rtl>).
	RANK = 8
	WIDTH = 1
Entity <FIFO> analyzed. Unit <FIFO> generated.

Analyzing generic Entity <INPUT_CONTROL.0> (Architecture <rtl>).
	WIDTH = 8
Entity <INPUT_CONTROL.0> analyzed. Unit <INPUT_CONTROL.0> generated.

Analyzing generic Entity <FIFO.2> (Architecture <rtl>).
	RANK = 8
	WIDTH = 8
Entity <FIFO.2> analyzed. Unit <FIFO.2> generated.

Analyzing generic Entity <LIMIT_REGISTER> (Architecture <rtl>).
	CONST = <u>1
Entity <LIMIT_REGISTER> analyzed. Unit <LIMIT_REGISTER> generated.

Analyzing generic Entity <LIMIT_REGISTER.1> (Architecture <rtl>).
	CONST = <u>0
Entity <LIMIT_REGISTER.1> analyzed. Unit <LIMIT_REGISTER.1> generated.

Analyzing Entity <ARITHMETIC_UNIT> (Architecture <rtl>).
Entity <ARITHMETIC_UNIT> analyzed. Unit <ARITHMETIC_UNIT> generated.

Analyzing Entity <CONVERGENCE_CHECK> (Architecture <rtl>).
Entity <CONVERGENCE_CHECK> analyzed. Unit <CONVERGENCE_CHECK> generated.

Analyzing Entity <FOLLOW_COUNTER> (Architecture <rtl>).
Entity <FOLLOW_COUNTER> analyzed. Unit <FOLLOW_COUNTER> generated.

Analyzing Entity <OUTPUT_UNIT> (Architecture <rtl>).
Entity <OUTPUT_UNIT> analyzed. Unit <OUTPUT_UNIT> generated.

Analyzing Entity <CONTEXT_MANAGER> (Architecture <rtl>).
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" line 118: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" line 133: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" line 137: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd" line 141: Index value(s) does not match array range, simulation mismatch.
Entity <CONTEXT_MANAGER> analyzed. Unit <CONTEXT_MANAGER> generated.

Analyzing Entity <DIVIDER> (Architecture <rtl>).
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd" line 308: Index value(s) does not match array range, simulation mismatch.
Entity <DIVIDER> analyzed. Unit <DIVIDER> generated.

Analyzing Entity <UPDATER> (Architecture <rtl>).
Entity <UPDATER> analyzed. Unit <UPDATER> generated.

Analyzing Entity <HALVING_MANAGER> (Architecture <rtl>).
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 71: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 73: Index value(s) does not match array range, simulation mismatch.
WARNING:Xst:1610 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 78: Width mismatch. <NUMERATOR2> has a width of 8 bits but assigned expression is 10-bit wide.
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd" line 108: Index value(s) does not match array range, simulation mismatch.
Entity <HALVING_MANAGER> analyzed. Unit <HALVING_MANAGER> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <HALVING_MANAGER>.
    Related source file is "C:/Xilinx/bin/ArithmeticCoder/HALVING_MANAGER.vhd".
    Found 3-bit 46-to-1 multiplexer for signal <$n0002> created at line 108.
    Found 3-bit 4-to-1 multiplexer for signal <$n0050>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0051>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0052>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0053>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0054>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0055>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0056>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0057>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0058>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0059>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0060>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0061>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0062>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0063>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0064>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0065>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0066>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0067>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0068>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0069>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0070>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0071>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0072>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0073>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0074>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0075>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0076>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0077>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0078>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0079>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0080>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0081>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0082>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0084>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0085>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0087>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0088>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0089>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0090>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0091>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0092>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0093>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0094>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0095>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0096>.
    Found 3-bit 4-to-1 multiplexer for signal <$n0097>.
    Found 3-bit addsub for signal <$n0098>.
    Found 3-bit addsub for signal <$n0100>.
    Found 3-bit addsub for signal <$n0101>.
    Found 3-bit addsub for signal <$n0102>.
    Found 3-bit addsub for signal <$n0103>.
    Found 3-bit addsub for signal <$n0104>.
    Found 3-bit addsub for signal <$n0105>.
    Found 3-bit addsub for signal <$n0106>.
    Found 3-bit addsub for signal <$n0107>.
    Found 3-bit addsub for signal <$n0108>.
    Found 3-bit addsub for signal <$n0109>.
    Found 3-bit addsub for signal <$n0110>.
    Found 3-bit addsub for signal <$n0111>.
    Found 3-bit addsub for signal <$n0112>.
    Found 3-bit addsub for signal <$n0113>.
    Found 3-bit addsub for signal <$n0114>.
    Found 3-bit addsub for signal <$n0115>.
    Found 3-bit addsub for signal <$n0116>.
    Found 3-bit addsub for signal <$n0117>.
    Found 3-bit addsub for signal <$n0118>.
    Found 3-bit addsub for signal <$n0119>.
    Found 3-bit addsub for signal <$n0120>.
    Found 3-bit addsub for signal <$n0121>.
    Found 3-bit addsub for signal <$n0122>.
    Found 3-bit addsub for signal <$n0123>.
    Found 3-bit addsub for signal <$n0124>.
    Found 3-bit addsub for signal <$n0125>.
    Found 3-bit addsub for signal <$n0126>.
    Found 3-bit addsub for signal <$n0127>.
    Found 3-bit addsub for signal <$n0128>.
    Found 3-bit addsub for signal <$n0129>.
    Found 3-bit addsub for signal <$n0130>.
    Found 3-bit addsub for signal <$n0131>.
    Found 3-bit addsub for signal <$n0132>.
    Found 3-bit addsub for signal <$n0133>.
    Found 3-bit addsub for signal <$n0134>.
    Found 3-bit addsub for signal <$n0135>.
    Found 3-bit addsub for signal <$n0136>.
    Found 3-bit addsub for signal <$n0137>.
    Found 3-bit addsub for signal <$n0138>.
    Found 3-bit addsub for signal <$n0139>.
    Found 3-bit addsub for signal <$n0140>.
    Found 3-bit addsub for signal <$n0141>.
    Found 3-bit addsub for signal <$n0142>.
    Found 3-bit addsub for signal <$n0143>.
    Found 3-bit addsub for signal <$n0144>.
    Found 8-bit comparator greater for signal <$n0147> created at line 99.
    Found 3-bit comparator greater for signal <$n0241> created at line 108.
    Found 1-bit register for signal <AFTER_TRIGGER>.
    Found 8-bit register for signal <DENOMINATOR>.
    Found 8-bit adder for signal <DENOMINATOR2>.
    Found 8-bit register for signal <NUMERATOR>.
    Found 8-bit adder for signal <NUMERATOR2>.
    Found 138-bit register for signal <SHIFTS>.
    Summary:
	inferred 139 D-type flip-flop(s).
	inferred  48 Adder/Subtractor(s).
	inferred   2 Comparator(s).
	inferred 141 Multiplexer(s).
Unit <HALVING_MANAGER> synthesized.


Synthesizing Unit <UPDATER>.
    Related source file is "C:/Xilinx/bin/ArithmeticCoder/UPDATER.vhd".
    Found 1-bit register for signal <UPDATE>.
    Found 8-bit 4-to-1 multiplexer for signal <DENOMINATOR_OUT>.
    Found 8-bit 4-to-1 multiplexer for signal <NUMERATOR_OUT>.
    Found 8-bit adder for signal <$n0009> created at line 50.
    Found 8-bit adder for signal <$n0011> created at line 72.
    Found 8-bit adder for signal <$n0012> created at line 83.
    Found 8-bit adder for signal <$n0013> created at line 61.
    Found 8-bit register for signal <DENOMINATOR2>.
    Found 8-bit register for signal <NUMERATOR1>.
    Found 8-bit register for signal <NUMERATOR2>.
    Found 8-bit register for signal <NUMERATOR3>.
    Found 8-bit register for signal <NUMERATOR4>.
    Found 1-bit xor2 for signal <UPDATE_SWITCH>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   4 Adder/Subtractor(s).
	inferred  16 Multiplexer(s).
Unit <UPDATER> synthesized.


Synthesizing Unit <DIVIDER>.
    Related source file is "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd".
WARNING:Xst:646 - Signal <PRODUCT<23:16>> is assigned but never used.
WARNING:Xst:646 - Signal <PRODUCT<7:0>> is assigned but never used.
    Found 254x16-bit ROM for signal <$n0002> created at line 308.
    Found 16x8-bit multiplier for signal <$n0003> created at line 315.
    Found 8-bit subtractor for signal <INDEX>.
    Found 8-bit register for signal <NUMERATOR2>.
    Found 24-bit register for signal <PRODUCT>.
    Found 16-bit register for signal <RECIPROCAL>.
    Summary:
	inferred   1 ROM(s).
	inferred  40 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
	inferred   1 Multiplier(s).
Unit <DIVIDER> synthesized.


Synthesizing Unit <FIFO_0>.
    Related source file is "C:/Xilinx/bin/ArithmeticCoder/FIFO.vhd".
    Found 256x8-bit dual-port distributed RAM for signal <GET_OUTPUT>.
    -----------------------------------------------------------------------
    | aspect ratio       | 256-word x 8-bit                    |          |
    | clock              | connected to signal <CLOCK>         | rise     |
    | write enable       | connected to signal <WRITE_ENABLE>  | high     |
    | address            | connected to signal <WRITE_ADDRESS> |          |
    | dual address       | connected to signal <READ_ADDRESS>  |          |
    | data in            | connected to signal <DATA_IN>       |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <DATA_OUT>      |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronously. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8-bit comparator equal for signal <$n0003> created at line 69.
    Found 8-bit up counter for signal <READ_ADDRESS>.
    Found 8-bit up counter for signal <WRITE_ADDRESS>.
    Summary:
	inferred   1 RAM(s).
	inferred   2 Counter(s).
	inferred   1 Comparator(s).
Unit <FIFO_0> synthesized.


Synthesizing Unit <FIFO>.
    Related source file is "C:/Xilinx/bin/ArithmeticCoder/FIFO.vhd".
    Found 256x1-bit dual-port distributed RAM for signal <GET_OUTPUT>.
    -----------------------------------------------------------------------
    | aspect ratio       | 256-word x 1-bit                    |          |
    | clock              | connected to signal <CLOCK>         | rise     |
    | write enable       | connected to signal <WRITE_ENABLE>  | high     |
    | address            | connected to signal <WRITE_ADDRESS> |          |
    | dual address       | connected to signal <READ_ADDRESS>  |          |
    | data in            | connected to signal <DATA_IN>       |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <DATA_OUT>      |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
INFO:Xst:1442 - HDL ADVISOR - The RAM contents appears to be read asynchronously. A synchronous read would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    Found 8-bit comparator equal for signal <$n0003> created at line 69.
    Found 8-bit up counter for signal <READ_ADDRESS>.
    Found 8-bit up counter for signal <WRITE_ADDRESS>.
    Summary:
	inferred   1 RAM(s).
	inferred   2 Counter(s).
	inferred   1 Comparator(s).
Unit <FIFO> synthesized.


Synthesizing Unit <CONTEXT_MANAGER>.
    Related source file is "C:/Xilinx/bin/ArithmeticCoder/CONTEXT_MANAGER.vhd".
    Found 46x16-bit dual-port block RAM for signal <PROBABILITY>.
    -----------------------------------------------------------------------
    | mode               | write-first                         |          |
    | aspect ratio       | 46-word x 16-bit                    |          |
    | clock              | connected to signal <CLOCK>         | rise     |
    | dual clock         | connected to signal <CLOCK>         | rise     |
    | dual enable        | connected to signal <SET>           | high     |
    | write enable       | connected to signal <LOAD_DATA>     | high     |
    | address            | connected to signal <OLD_CONTEXT>   |          |
    | dual address       | connected to signal <CONTEXT_NUMBER> |          |
    | data in            | connected to signal <NEWPROB>       |          |
    | data out           | not connected                       |          |
    | dual data out      | connected to signal <RATIO>         |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
    Found 1-bit 46-to-1 multiplexer for signal <$n0003> created at line 141.
    Found 1-bit register for signal <CONTEXT_VALID>.
    Found 2-bit register for signal <DATA_READY>.
    Found 6-bit register for signal <OLD_CONTEXT>.
    Found 6-bit register for signal <READ_ADDRESS>.
    Found 46-bit register for signal <RESET_FLAGS>.
    Summary:
	inferred   1 RAM(s).
	inferred  61 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <CONTEXT_MANAGER> synthesized.


Synthesizing Unit <OUTPUT_UNIT>.
    Related source file is "C:/Xilinx/bin/ArithmeticCoder/OUTPUT_UNIT.vhd".
    Found 1-bit register for signal <DELAYED>.
    Found 1-bit xor2 for signal <OUTVALUE>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <OUTPUT_UNIT> synthesized.


Synthesizing Unit <FOLLOW_COUNTER>.
    Related source file is "C:/Xilinx/bin/ArithmeticCoder/FOLLOW_COUNTER.vhd".
    Found 8-bit comparator lessequal for signal <$n0003> created at line 30.
    Found 8-bit comparator greater for signal <$n0004> created at line 39.
    Found 8-bit updown counter for signal <NUMBER>.
    Summary:
	inferred   1 Counter(s).
	inferred   2 Comparator(s).
Unit <FOLLOW_COUNTER> synthesized.


Synthesizing Unit <CONVERGENCE_CHECK>.
    Related source file is "C:/Xilinx/bin/ArithmeticCoder/CONVERGENCE_CHECK.vhd".
Unit <CONVERGENCE_CHECK> synthesized.


Synthesizing Unit <ARITHMETIC_UNIT>.
    Related source file is "C:/Xilinx/bin/ArithmeticCoder/ARITHMETIC_UNIT.vhd".
WARNING:Xst:646 - Signal <PRODUCT<7:0>> is assigned but never used.
WARNING:Xst:646 - Signal <DIFFERENCE3<16>> is assigned but never used.
WARNING:Xst:646 - Signal <DIFFERENCE4<16>> is assigned but never used.
WARNING:Xst:646 - Signal <RESULT0<16>> is assigned but never used.
    Found 17x8-bit multiplier for signal <$n0000> created at line 48.
    Found 1-bit register for signal <DELAY1>.
    Found 17-bit register for signal <DIFFERENCE1>.
    Found 17-bit adder for signal <DIFFERENCE2>.
    Found 17-bit subtractor for signal <DIFFERENCE3>.
    Found 17-bit subtractor for signal <DIFFERENCE4>.
    Found 17-bit register for signal <LOW2>.
    Found 25-bit register for signal <PRODUCT>.
    Found 17-bit adder for signal <RESULT>.
    Found 17-bit subtractor for signal <RESULT0>.
    Summary:
	inferred  60 D-type flip-flop(s).
	inferred   5 Adder/Subtractor(s).
	inferred   1 Multiplier(s).
Unit <ARITHMETIC_UNIT> synthesized.


Synthesizing Unit <LIMIT_REGISTER_0>.
    Related source file is "C:/Xilinx/bin/ArithmeticCoder/REGISTER.vhd".
    Found 16-bit register for signal <Q>.
    Summary:
	inferred  16 D-type flip-flop(s).
Unit <LIMIT_REGISTER_0> synthesized.


Synthesizing Unit <LIMIT_REGISTER>.
    Related source file is "C:/Xilinx/bin/ArithmeticCoder/REGISTER.vhd".
    Found 16-bit register for signal <Q>.
    Summary:
	inferred  16 D-type flip-flop(s).
Unit <LIMIT_REGISTER> synthesized.


Synthesizing Unit <INPUT_CONTROL_0>.
    Related source file is "C:/Xilinx/bin/ArithmeticCoder/INPUT_CONTROL.vhd".
    Found 8-bit register for signal <HELD>.
    Found 8-bit 4-to-1 multiplexer for signal <OUTPUT>.
    Summary:
	inferred   8 D-type flip-flop(s).
	inferred   8 Multiplexer(s).
Unit <INPUT_CONTROL_0> synthesized.


Synthesizing Unit <INPUT_CONTROL>.
    Related source file is "C:/Xilinx/bin/ArithmeticCoder/INPUT_CONTROL.vhd".
    Found 1-bit register for signal <HELD<0>>.
    Found 1-bit 4-to-1 multiplexer for signal <OUTPUT<0>>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <INPUT_CONTROL> synthesized.


Synthesizing Unit <arithmeticcoder>.
    Related source file is "C:/Xilinx/bin/ArithmeticCoder/ARITHMETICCODER.vhd".
WARNING:Xst:646 - Signal <HIGH_OUT<13:0>> is assigned but never used.
    Found 1-bit register for signal <ALLOWHALVING>.
    Found 1-bit register for signal <DELAYED_CHECK>.
    Found 1-bit register for signal <FLUSH_ENCODER>.
    Found 1-bit register for signal <HOLDCONTEXT>.
    Found 1-bit register for signal <LOCK>.
    Summary:
	inferred   5 D-type flip-flop(s).
Unit <arithmeticcoder> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
INFO:Xst:1647 - Data output of ROM <Mrom__n0002> in block <DIVIDER> is tied to register <RECIPROCAL> in block <DIVIDER>.
INFO:Xst:1650 - The register is removed and the ROM is implemented as read-only block RAM.
Advanced multiplier inference ...
    Found registered multiplier on signal <_n0000>:
	- 1 register level(s) found in a register connected to the multiplier macro ouput.
	  Pushing register(s) into the multiplier macro.
    Found registered multiplier on signal <_n0003>:
	- 1 register level(s) found in a register connected to the multiplier macro ouput.
	  Pushing register(s) into the multiplier macro.
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Block RAMs                       : 2
 254x16-bit single-port block RAM  : 1
 46x16-bit dual-port block RAM     : 1
# LUT RAMs                         : 2
 256x1-bit dual-port distributed RAM: 1
 256x8-bit dual-port distributed RAM: 1
# Multipliers                      : 2
 16x8-bit registered multiplier    : 1
 17x8-bit registered multiplier    : 1
# Adders/Subtractors               : 58
 17-bit adder                      : 2
 17-bit subtractor                 : 3
 3-bit addsub                      : 46
 8-bit adder                       : 6
 8-bit subtractor                  : 1
# Counters                         : 5
 8-bit up counter                  : 4
 8-bit updown counter              : 1
# Registers                        : 166
 1-bit register                    : 107
 17-bit register                   : 2
 3-bit register                    : 46
 6-bit register                    : 2
 8-bit register                    : 9
# Comparators                      : 6
 3-bit comparator greater          : 1
 8-bit comparator equal            : 2
 8-bit comparator greater          : 2
 8-bit comparator lessequal        : 1
# Multiplexers                     : 52
 1-bit 4-to-1 multiplexer          : 1
 1-bit 46-to-1 multiplexer         : 1
 3-bit 4-to-1 multiplexer          : 46
 3-bit 46-to-1 multiplexer         : 1
 8-bit 4-to-1 multiplexer          : 3
# Xors                             : 2
 1-bit xor2                        : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <LOW2_16> (without init value) has a constant value of 0 in block <ARITHMETIC_UNIT>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DIFFERENCE1_16> (without init value) has a constant value of 0 in block <ARITHMETIC_UNIT>.
WARNING:Xst:1988 - Unit <FOLLOW_COUNTER>: instances <Mcompar__n0004>, <Mcompar__n0003> of unit <LPM_COMPARE_5> and unit <LPM_COMPARE_4> are dual, second instance is removed

Optimizing unit <arithmeticcoder> ...

Optimizing unit <CONTEXT_MANAGER> ...

Optimizing unit <CONVERGENCE_CHECK> ...

Optimizing unit <INPUT_CONTROL_0> ...

Optimizing unit <INPUT_CONTROL> ...

Optimizing unit <HALVING_MANAGER> ...

Optimizing unit <UPDATER> ...

Optimizing unit <DIVIDER> ...

Optimizing unit <FIFO_0> ...

Optimizing unit <FIFO> ...

Optimizing unit <FOLLOW_COUNTER> ...

Optimizing unit <OUTPUT_UNIT> ...

Optimizing unit <ARITHMETIC_UNIT> ...

Optimizing unit <LIMIT_REGISTER_0> ...

Optimizing unit <LIMIT_REGISTER> ...
Loading device for application Rf_Device from file '2v2000.nph' in environment C:/Xilinx.

Mapping all equations...
WARNING:Xst:637 - Naming conflict between signal DATA_OUT<7> of unit CONTEXT_BUFFER and signal CONTEXT_BUFFER_DATA_OUT<7> of unit arithmeticcoder : renaming CONTEXT_BUFFER_DATA_OUT<7> to CONTEXT_BUFFER_DATA_OUT<7>1.
WARNING:Xst:637 - Naming conflict between signal DATA_OUT<6> of unit CONTEXT_BUFFER and signal CONTEXT_BUFFER_DATA_OUT<6> of unit arithmeticcoder : renaming CONTEXT_BUFFER_DATA_OUT<6> to CONTEXT_BUFFER_DATA_OUT<6>1.
WARNING:Xst:637 - Naming conflict between signal DATA_OUT<5> of unit CONTEXT_BUFFER and signal CONTEXT_BUFFER_DATA_OUT<5> of unit arithmeticcoder : renaming CONTEXT_BUFFER_DATA_OUT<5> to CONTEXT_BUFFER_DATA_OUT<5>1.
WARNING:Xst:637 - Naming conflict between signal DATA_OUT<4> of unit CONTEXT_BUFFER and signal CONTEXT_BUFFER_DATA_OUT<4> of unit arithmeticcoder : renaming CONTEXT_BUFFER_DATA_OUT<4> to CONTEXT_BUFFER_DATA_OUT<4>1.
WARNING:Xst:637 - Naming conflict between signal DATA_OUT<3> of unit CONTEXT_BUFFER and signal CONTEXT_BUFFER_DATA_OUT<3> of unit arithmeticcoder : renaming CONTEXT_BUFFER_DATA_OUT<3> to CONTEXT_BUFFER_DATA_OUT<3>1.
WARNING:Xst:637 - Naming conflict between signal DATA_OUT<2> of unit CONTEXT_BUFFER and signal CONTEXT_BUFFER_DATA_OUT<2> of unit arithmeticcoder : renaming CONTEXT_BUFFER_DATA_OUT<2> to CONTEXT_BUFFER_DATA_OUT<2>1.
WARNING:Xst:637 - Naming conflict between signal DATA_OUT<1> of unit CONTEXT_BUFFER and signal CONTEXT_BUFFER_DATA_OUT<1> of unit arithmeticcoder : renaming CONTEXT_BUFFER_DATA_OUT<1> to CONTEXT_BUFFER_DATA_OUT<1>1.
WARNING:Xst:637 - Naming conflict between signal DATA_OUT<0> of unit CONTEXT_BUFFER and signal CONTEXT_BUFFER_DATA_OUT<0> of unit arithmeticcoder : renaming CONTEXT_BUFFER_DATA_OUT<0> to CONTEXT_BUFFER_DATA_OUT<0>1.
WARNING:Xst:637 - Naming conflict between signal SHIFT_ALL of unit DIFFERENCE and signal DIFFERENCE_SHIFT_ALL of unit arithmeticcoder : renaming DIFFERENCE_SHIFT_ALL to DIFFERENCE_SHIFT_ALL1.
Building and optimizing final netlist ...
Register <PROBABILITY_PROBUPDATE_UPDATE> equivalent to <PROBABILITY_DATA_READY_0> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_5> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_5> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_7> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_7> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_6> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_6> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_0> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_0> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_1> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_1> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_2> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_2> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_3> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_3> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_4> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_4> has been removed
Found area constraint ratio of 100 (+ 5) on block arithmeticcoder, actual ratio is 6.
FlipFlop ARITH_DELAY1 has been replicated 1 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_0 has been replicated 15 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_1 has been replicated 15 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_2 has been replicated 15 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_3 has been replicated 15 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_4 has been replicated 5 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_5 has been replicated 3 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_WRITE_ADDRESS_0 has been replicated 1 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_WRITE_ADDRESS_1 has been replicated 1 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_WRITE_ADDRESS_2 has been replicated 1 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_WRITE_ADDRESS_3 has been replicated 1 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_WRITE_ADDRESS_4 has been replicated 1 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_WRITE_ADDRESS_5 has been replicated 1 time(s)
FlipFlop INBUFFER_STORAGE_WRITE_ADDRESS_0 has been replicated 1 time(s)
FlipFlop INBUFFER_STORAGE_WRITE_ADDRESS_1 has been replicated 1 time(s)
FlipFlop INBUFFER_STORAGE_WRITE_ADDRESS_2 has been replicated 1 time(s)
FlipFlop INBUFFER_STORAGE_WRITE_ADDRESS_3 has been replicated 1 time(s)

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : arithmeticcoder.ngr
Top Level Output File Name         : arithmeticcoder
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 16

Macro Statistics :
# RAM                              : 4
#      254x16-bit single-port block RAM: 1
#      256x1-bit dual-port distributed RAM: 1
#      256x8-bit dual-port distributed RAM: 1
#      46x16-bit dual-port block RAM: 1
# Registers                        : 227
#      1-bit register              : 171
#      17-bit register             : 2
#      3-bit register              : 46
#      6-bit register              : 2
#      8-bit register              : 6
# Multiplexers                     : 52
#      1-bit 4-to-1 multiplexer    : 1
#      1-bit 46-to-1 multiplexer   : 1
#      3-bit 4-to-1 multiplexer    : 46
#      3-bit 46-to-1 multiplexer   : 1
#      8-bit 4-to-1 multiplexer    : 3
# Adders/Subtractors               : 17
#      17-bit adder                : 2
#      17-bit subtractor           : 3
#      8-bit adder                 : 11
#      8-bit subtractor            : 1
# Multipliers                      : 2
#      16x8-bit registered multiplier: 1
#      17x8-bit registered multiplier: 1
# Comparators                      : 6
#      3-bit comparator greater    : 1
#      8-bit comparator equal      : 2
#      8-bit comparator greater    : 2
#      8-bit comparator lessequal  : 1
# Xors                             : 92
#      1-bit xor3                  : 92

Cell Usage :
# BELS                             : 1336
#      GND                         : 1
#      INV                         : 36
#      LUT1                        : 55
#      LUT1_L                      : 7
#      LUT2                        : 58
#      LUT2_D                      : 1
#      LUT2_L                      : 10
#      LUT3                        : 147
#      LUT3_D                      : 9
#      LUT3_L                      : 142
#      LUT4                        : 252
#      LUT4_D                      : 24
#      LUT4_L                      : 185
#      MUXCY                       : 161
#      MUXF5                       : 62
#      MUXF6                       : 20
#      MUXF7                       : 8
#      MUXF8                       : 4
#      VCC                         : 1
#      XORCY                       : 153
# FlipFlops/Latches                : 471
#      FD                          : 7
#      FDE                         : 86
#      FDR                         : 40
#      FDRE                        : 280
#      FDRSE                       : 2
#      FDS                         : 7
#      FDSE                        : 49
# RAMS                             : 38
#      RAM64X1D                    : 36
#      RAMB16_S36                  : 1
#      RAMB16_S36_S36              : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 15
#      IBUF                        : 12
#      OBUF                        : 3
# MULTs                            : 2
#      MULT18X18S                  : 2
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2v2000bg575-6 

 Number of Slices:                     719  out of  10752     6%  
 Number of Slice Flip Flops:           471  out of  21504     2%  
 Number of 4 input LUTs:              1034  out of  21504     4%  
 Number of bonded IOBs:                 16  out of    408     3%  
 Number of BRAMs:                        2  out of     56     3%  
 Number of MULT18X18s:                   2  out of     56     3%  
 Number of GCLKs:                        1  out of     16     6%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLOCK                              | BUFGP                  | 510   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 16.315ns (Maximum Frequency: 61.291MHz)
   Minimum input arrival time before clock: 15.562ns
   Maximum output required time after clock: 8.122ns
   Maximum combinational path delay: 7.705ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLOCK'
  Clock period: 16.315ns (frequency: 61.291MHz)
  Total number of paths / destination ports: 23899270 / 1400
-------------------------------------------------------------------------
Delay:               16.315ns (Levels of Logic = 28)
  Source:            INBUFFER_STORAGE_READ_ADDRESS_1 (FF)
  Destination:       PROBABILITY_PROBUPDATE_NUMERATOR4_7 (FF)
  Source Clock:      CLOCK rising
  Destination Clock: CLOCK rising

  Data Path: INBUFFER_STORAGE_READ_ADDRESS_1 to PROBABILITY_PROBUPDATE_NUMERATOR4_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDRE:C->Q            18   0.449   0.788  INBUFFER_STORAGE_READ_ADDRESS_1 (INBUFFER_STORAGE_READ_ADDRESS_1)
     LUT4_L:I3->LO         1   0.347   0.000  INBUFFER_STORAGE_Eq_stagelut (INBUFFER_STORAGE_N4)
     MUXCY:S->O            1   0.235   0.000  INBUFFER_STORAGE_Eq_stagecy (INBUFFER_STORAGE_Eq_stage_cyo)
     MUXCY:CI->O           1   0.042   0.000  INBUFFER_STORAGE_Eq_stagecy_rn_0 (INBUFFER_STORAGE_Eq_stage_cyo1)
     MUXCY:CI->O           1   0.042   0.000  INBUFFER_STORAGE_Eq_stagecy_rn_1 (INBUFFER_STORAGE_Eq_stage_cyo2)
     MUXCY:CI->O          10   0.601   0.819  INBUFFER_STORAGE_Eq_stagecy_rn_2 (INBUFFER_FIFO_EMPTY)
     LUT2:I1->O            1   0.347   0.547  BUFFER_INPUT1_SW1 (N835)
     LUT4_D:I1->O         12   0.347   0.715  INBUFFER_SENDING1 (DATA_AVAILABLE)
     LUT4_D:I2->O         13   0.347   0.738  CONTEXT_BUFFER_Ker31 (CONTEXT_BUFFER_N3)
     LUT4_D:I3->O          6   0.347   0.613  CONTEXT_BUFFER_DATA_OUT<6>_SW0_SW0 (N849)
     LUT3:I2->O            9   0.347   0.665  CONTEXT_BUFFER_DATA_OUT<6>_2 (CONTEXT_BUFFER_DATA_OUT<6>_1)
     LUT3_L:I2->LO         1   0.347   0.000  PROBABILITY_REFRESH_CONTEXT<4>5 (PROBABILITY_REFRESH_MUX_BLOCK_N6)
     MUXF5:I0->O           1   0.345   0.000  PROBABILITY_REFRESH_CONTEXT<1>_rn_1 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<1>_MUXF52)
     MUXF6:I1->O           1   0.354   0.000  PROBABILITY_REFRESH_CONTEXT<0>_rn_0 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF61)
     MUXF7:I0->O           1   0.354   0.000  PROBABILITY_REFRESH_CONTEXT<2> (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF7)
     MUXF8:I1->O           1   0.354   0.548  PROBABILITY_REFRESH_CONTEXT<3> (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<3>_MUXF8)
     LUT4_L:I1->LO         1   0.347   0.132  PROBABILITY_REFRESH__n0241106 (CHOICE621)
     LUT4:I3->O           19   0.347   0.792  PROBABILITY_REFRESH__n0241109 (PROBABILITY_REFRESH__n0241)
     LUT4_D:I2->LO         2   0.347   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0013<0>lut (N991)
     MUXCY:S->O            1   0.235   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0013<0>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<0>_cyo)
     MUXCY:CI->O           1   0.042   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0013<1>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<1>_cyo)
     MUXCY:CI->O           1   0.042   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0013<2>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<2>_cyo)
     MUXCY:CI->O           1   0.042   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0013<3>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<3>_cyo)
     MUXCY:CI->O           1   0.042   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0013<4>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<4>_cyo)
     MUXCY:CI->O           1   0.042   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0013<5>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<5>_cyo)
     XORCY:CI->O           2   0.824   0.744  PROBABILITY_PROBUPDATE_UPDATER__n0013<6>_xor (PROBABILITY_PROBUPDATE__n0013<6>)
     LUT1_L:I0->LO         1   0.347   0.000  PROBABILITY_PROBUPDATE__n0013<6>_rt (PROBABILITY_PROBUPDATE__n0013<6>_rt)
     MUXCY:S->O            0   0.235   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0011<6>cy (PROBABILITY_PROBUPDATE_UPDATER__n0011<6>_cyo)
     XORCY:CI->O           1   0.824   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0011<7>_xor (PROBABILITY_PROBUPDATE__n0011<7>)
     FDR:D                     0.293          PROBABILITY_PROBUPDATE_NUMERATOR4_7
    ----------------------------------------
    Total                     16.315ns (9.214ns logic, 7.101ns route)
                                       (56.5% logic, 43.5% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLOCK'
  Total number of paths / destination ports: 1496299 / 1156
-------------------------------------------------------------------------
Offset:              15.562ns (Levels of Logic = 24)
  Source:            RESET (PAD)
  Destination:       PROBABILITY_PROBUPDATE_NUMERATOR4_7 (FF)
  Destination Clock: CLOCK rising

  Data Path: RESET to PROBABILITY_PROBUPDATE_NUMERATOR4_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O           444   0.653   1.818  RESET_IBUF (RESET_IBUF)
     LUT4:I0->O            8   0.347   0.648  OUTPUT_SENDING1 (SENDING_OBUF)
     LUT4_D:I2->O         12   0.347   0.715  INBUFFER_SENDING1 (DATA_AVAILABLE)
     LUT4_D:I2->O         13   0.347   0.738  CONTEXT_BUFFER_Ker31 (CONTEXT_BUFFER_N3)
     LUT4_D:I3->O          6   0.347   0.613  CONTEXT_BUFFER_DATA_OUT<6>_SW0_SW0 (N849)
     LUT3:I2->O            9   0.347   0.665  CONTEXT_BUFFER_DATA_OUT<6>_2 (CONTEXT_BUFFER_DATA_OUT<6>_1)
     LUT3_L:I2->LO         1   0.347   0.000  PROBABILITY_REFRESH_CONTEXT<4>5 (PROBABILITY_REFRESH_MUX_BLOCK_N6)
     MUXF5:I0->O           1   0.345   0.000  PROBABILITY_REFRESH_CONTEXT<1>_rn_1 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<1>_MUXF52)
     MUXF6:I1->O           1   0.354   0.000  PROBABILITY_REFRESH_CONTEXT<0>_rn_0 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF61)
     MUXF7:I0->O           1   0.354   0.000  PROBABILITY_REFRESH_CONTEXT<2> (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF7)
     MUXF8:I1->O           1   0.354   0.548  PROBABILITY_REFRESH_CONTEXT<3> (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<3>_MUXF8)
     LUT4_L:I1->LO         1   0.347   0.132  PROBABILITY_REFRESH__n0241106 (CHOICE621)
     LUT4:I3->O           19   0.347   0.792  PROBABILITY_REFRESH__n0241109 (PROBABILITY_REFRESH__n0241)
     LUT4_D:I2->LO         2   0.347   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0013<0>lut (N991)
     MUXCY:S->O            1   0.235   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0013<0>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<0>_cyo)
     MUXCY:CI->O           1   0.042   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0013<1>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<1>_cyo)
     MUXCY:CI->O           1   0.042   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0013<2>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<2>_cyo)
     MUXCY:CI->O           1   0.042   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0013<3>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<3>_cyo)
     MUXCY:CI->O           1   0.042   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0013<4>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<4>_cyo)
     MUXCY:CI->O           1   0.042   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0013<5>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<5>_cyo)
     XORCY:CI->O           2   0.824   0.744  PROBABILITY_PROBUPDATE_UPDATER__n0013<6>_xor (PROBABILITY_PROBUPDATE__n0013<6>)
     LUT1_L:I0->LO         1   0.347   0.000  PROBABILITY_PROBUPDATE__n0013<6>_rt (PROBABILITY_PROBUPDATE__n0013<6>_rt)
     MUXCY:S->O            0   0.235   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0011<6>cy (PROBABILITY_PROBUPDATE_UPDATER__n0011<6>_cyo)
     XORCY:CI->O           1   0.824   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0011<7>_xor (PROBABILITY_PROBUPDATE__n0011<7>)
     FDR:D                     0.293          PROBABILITY_PROBUPDATE_NUMERATOR4_7
    ----------------------------------------
    Total                     15.562ns (8.151ns logic, 7.411ns route)
                                       (52.4% logic, 47.6% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLOCK'
  Total number of paths / destination ports: 44 / 3
-------------------------------------------------------------------------
Offset:              8.122ns (Levels of Logic = 5)
  Source:            OUTPUT_DELAYED (FF)
  Destination:       DATA_OUT (PAD)
  Source Clock:      CLOCK rising

  Data Path: OUTPUT_DELAYED to DATA_OUT
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q              20   0.449   0.934  OUTPUT_DELAYED (OUTPUT_DELAYED)
     LUT2_L:I1->LO         1   0.347   0.127  CONVERGENCE_TEST1 (CONVERGENCE_TEST)
     LUT4:I2->O            2   0.347   0.684  TRIGGER_OUTPUT1 (TRIGGER_OUTPUT)
     LUT2:I1->O            1   0.347   0.414  OUTPUT_DATA_OUT1 (OUTPUT_N0)
     LUT4:I3->O            1   0.347   0.383  OUTPUT_DATA_OUT2 (DATA_OUT_OBUF)
     OBUF:I->O                 3.743          DATA_OUT_OBUF (DATA_OUT)
    ----------------------------------------
    Total                      8.122ns (5.580ns logic, 2.542ns route)
                                       (68.7% logic, 31.3% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 2 / 2
-------------------------------------------------------------------------
Delay:               7.705ns (Levels of Logic = 4)
  Source:            RESET (PAD)
  Destination:       DATA_OUT (PAD)

  Data Path: RESET to DATA_OUT
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O           444   0.653   1.818  RESET_IBUF (RESET_IBUF)
     LUT2:I0->O            1   0.347   0.414  OUTPUT_DATA_OUT1 (OUTPUT_N0)
     LUT4:I3->O            1   0.347   0.383  OUTPUT_DATA_OUT2 (DATA_OUT_OBUF)
     OBUF:I->O                 3.743          DATA_OUT_OBUF (DATA_OUT)
    ----------------------------------------
    Total                      7.705ns (5.090ns logic, 2.615ns route)
                                       (66.1% logic, 33.9% route)

=========================================================================
CPU : 32.67 / 33.06 s | Elapsed : 33.00 / 33.00 s
 
--> 

Total memory usage is 129340 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   29 (   0 filtered)
Number of infos    :    5 (   0 filtered)

@


1.1
log
@Adaptive probability models now implemented in the decoder. Testbench for decoding added. Synthesis reports added to documentation section
@
text
@d4 1
a4 1
CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s
d7 1
a7 1
CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 0.00 s
d101 1
a101 2
Entity <updater> compiled.
Entity <updater> (Architecture <rtl>) compiled.
d168 1
d171 1
d175 1
a175 1
WARNING:Xst:790 - "C:/Xilinx/bin/ArithmeticCoder/Divider.vhd" line 1079: Index value(s) does not match array range, simulation mismatch.
d185 1
d289 1
a289 1
    Found 10-bit comparator greater for signal <$n0147> created at line 99.
d292 4
a295 4
    Found 10-bit register for signal <DENOMINATOR>.
    Found 10-bit adder for signal <DENOMINATOR2>.
    Found 10-bit register for signal <NUMERATOR>.
    Found 10-bit adder for signal <NUMERATOR2>.
a306 1
WARNING:Xst:1780 - Signal <HALVING_ALLOWED> is never used or assigned.
d308 11
a318 11
    Found 10-bit 4-to-1 multiplexer for signal <DENOMINATOR_OUT>.
    Found 10-bit 4-to-1 multiplexer for signal <NUMERATOR_OUT>.
    Found 10-bit adder for signal <$n0009> created at line 51.
    Found 10-bit adder for signal <$n0011> created at line 73.
    Found 10-bit adder for signal <$n0012> created at line 84.
    Found 10-bit adder for signal <$n0013> created at line 62.
    Found 10-bit register for signal <DENOMINATOR2>.
    Found 10-bit register for signal <NUMERATOR1>.
    Found 10-bit register for signal <NUMERATOR2>.
    Found 10-bit register for signal <NUMERATOR3>.
    Found 10-bit register for signal <NUMERATOR4>.
d323 1
a323 1
	inferred  20 Multiplexer(s).
d329 8
a336 11
WARNING:Xst:646 - Signal <TOTAL<41:32>> is assigned but never used.
WARNING:Xst:646 - Signal <TOTAL<21:0>> is assigned but never used.
    Found 1022x32-bit ROM for signal <$n0002> created at line 1079.
    Found 16x10-bit multiplier for signal <$n0003> created at line 1086.
    Found 16x10-bit multiplier for signal <$n0004> created at line 1093.
    Found 10-bit subtractor for signal <INDEX>.
    Found 10-bit register for signal <NUMERATOR2>.
    Found 26-bit register for signal <PRODUCT1>.
    Found 26-bit register for signal <PRODUCT2>.
    Found 32-bit register for signal <RECIPROCAL>.
    Found 42-bit adder for signal <TOTAL>.
d339 3
a341 3
	inferred  84 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   2 Multiplier(s).
d397 1
a397 1
    Found 46x20-bit dual-port block RAM for signal <PROBABILITY>.
d400 1
a400 1
    | aspect ratio       | 46-word x 20-bit                    |          |
d412 1
a412 1
    Found 1-bit 64-to-1 multiplexer for signal <$n0003> created at line 141.
d417 1
a417 1
    Found 64-bit register for signal <RESET_FLAGS>.
d420 1
a420 1
	inferred  79 D-type flip-flop(s).
d452 1
a452 1
WARNING:Xst:646 - Signal <PRODUCT<9:0>> is assigned but never used.
d456 1
a456 1
    Found 17x10-bit multiplier for signal <$n0000> created at line 48.
d463 1
a463 1
    Found 27-bit register for signal <PRODUCT>.
d467 1
a467 1
	inferred  62 D-type flip-flop(s).
a536 3
    Found registered multiplier on signal <_n0004>:
	- 1 register level(s) found in a register connected to the multiplier macro ouput.
	  Pushing register(s) into the multiplier macro.
d545 2
a546 2
 1022x32-bit single-port block RAM : 1
 46x20-bit dual-port block RAM     : 1
d550 4
a553 6
# Multipliers                      : 3
 16x10-bit registered multiplier   : 2
 17x10-bit registered multiplier   : 1
# Adders/Subtractors               : 59
 10-bit adder                      : 6
 10-bit subtractor                 : 1
d557 2
a558 1
 42-bit adder                      : 1
d562 2
a563 3
# Registers                        : 184
 1-bit register                    : 125
 10-bit register                   : 8
d567 1
a567 1
 8-bit register                    : 1
a568 1
 10-bit comparator greater         : 1
d571 1
a571 1
 8-bit comparator greater          : 1
d575 1
a575 2
 1-bit 64-to-1 multiplexer         : 1
 10-bit 4-to-1 multiplexer         : 2
d578 1
a578 1
 8-bit 4-to-1 multiplexer          : 1
d634 1
d636 1
a636 2
Register <PROBABILITY_DIVISION_NUMERATOR2_9> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_9> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_8> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_8> has been removed
a641 2
Register <PROBABILITY_DIVISION_NUMERATOR2_5> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_5> has been removed
Register <PROBABILITY_DIVISION_NUMERATOR2_6> equivalent to <PROBABILITY_PROBUPDATE_NUMERATOR1_6> has been removed
d644 6
a649 6
FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_0 has been replicated 14 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_1 has been replicated 14 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_2 has been replicated 14 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_3 has been replicated 14 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_4 has been replicated 7 time(s)
FlipFlop CONTEXT_BUFFER_STORAGE_READ_ADDRESS_5 has been replicated 2 time(s)
d676 1
a676 1
#      1022x32-bit single-port block RAM: 1
d679 3
a681 3
#      46x20-bit dual-port block RAM: 1
# Registers                        : 261
#      1-bit register              : 205
d688 1
a688 2
#      1-bit 64-to-1 multiplexer   : 1
#      10-bit 4-to-1 multiplexer   : 2
d691 2
a692 4
#      8-bit 4-to-1 multiplexer    : 1
# Adders/Subtractors               : 18
#      10-bit adder                : 6
#      10-bit subtractor           : 1
d695 5
a699 5
#      42-bit adder                : 1
#      8-bit adder                 : 5
# Multipliers                      : 3
#      16x10-bit registered multiplier: 2
#      17x10-bit registered multiplier: 1
a700 1
#      10-bit comparator greater   : 1
d703 1
a703 1
#      8-bit comparator greater    : 1
d709 1
a709 1
# BELS                             : 1489
d712 16
a727 16
#      LUT1                        : 64
#      LUT1_L                      : 9
#      LUT2                        : 60
#      LUT2_D                      : 2
#      LUT2_L                      : 2
#      LUT3                        : 108
#      LUT3_D                      : 10
#      LUT3_L                      : 246
#      LUT4                        : 272
#      LUT4_D                      : 33
#      LUT4_L                      : 158
#      MUXCY                       : 196
#      MUXF5                       : 69
#      MUXF6                       : 23
#      MUXF7                       : 10
#      MUXF8                       : 5
d729 2
a730 2
#      XORCY                       : 184
# FlipFlops/Latches                : 500
d733 2
a734 2
#      FDR                         : 50
#      FDRE                        : 281
d737 2
a738 2
#      FDSE                        : 67
# RAMS                             : 39
d740 1
a740 1
#      RAMB16_S18                  : 2
d747 2
a748 2
# MULTs                            : 3
#      MULT18X18S                  : 3
d756 3
a758 3
 Number of Slices:                     750  out of  10752     6%  
 Number of Slice Flip Flops:           500  out of  21504     2%  
 Number of 4 input LUTs:              1108  out of  21504     5%  
d760 2
a761 2
 Number of BRAMs:                        3  out of     56     5%  
 Number of MULT18X18s:                   3  out of     56     5%  
d777 1
a777 1
CLOCK                              | BUFGP                  | 540   |
d784 2
a785 2
   Minimum period: 16.221ns (Maximum Frequency: 61.648MHz)
   Minimum input arrival time before clock: 15.527ns
d787 1
a787 1
   Maximum combinational path delay: 7.764ns
d795 2
a796 2
  Clock period: 16.221ns (frequency: 61.648MHz)
  Total number of paths / destination ports: 30998811 / 1448
d798 1
a798 1
Delay:               16.221ns (Levels of Logic = 30)
d800 1
a800 1
  Destination:       PROBABILITY_PROBUPDATE_NUMERATOR4_9 (FF)
d804 1
a804 1
  Data Path: INBUFFER_STORAGE_READ_ADDRESS_1 to PROBABILITY_PROBUPDATE_NUMERATOR4_9
d814 1
a814 1
     LUT2:I1->O            1   0.347   0.547  BUFFER_INPUT1_SW1 (N827)
d816 2
a817 2
     LUT4:I2->O            8   0.347   0.653  CONTEXT_BUFFER_Ker01 (CONTEXT_BUFFER_N01)
     LUT4_D:I3->O          6   0.347   0.613  CONTEXT_BUFFER_DATA_OUT<6>_SW0_SW0 (N829)
d819 4
a822 4
     LUT3_L:I2->LO         1   0.347   0.000  PROBABILITY_REFRESH_CONTEXT<4>3 (PROBABILITY_REFRESH_MUX_BLOCK_N4)
     MUXF5:I0->O           1   0.345   0.000  PROBABILITY_REFRESH_CONTEXT<1>_rn_0 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<1>_MUXF51)
     MUXF6:I0->O           1   0.354   0.000  PROBABILITY_REFRESH_CONTEXT<0> (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF6)
     MUXF7:I1->O           1   0.354   0.000  PROBABILITY_REFRESH_CONTEXT<2> (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF7)
d824 3
a826 3
     LUT4_D:I1->LO         1   0.347   0.132  PROBABILITY_REFRESH__n0241106 (N969)
     LUT4:I3->O           11   0.347   0.699  PROBABILITY_REFRESH__n0241109_1 (PROBABILITY_REFRESH__n0241109)
     LUT4_D:I2->LO         2   0.347   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0013<0>lut (N979)
d833 5
a837 7
     MUXCY:CI->O           1   0.042   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0013<6>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<6>_cyo)
     MUXCY:CI->O           1   0.042   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0013<7>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<7>_cyo)
     XORCY:CI->O           2   0.824   0.744  PROBABILITY_PROBUPDATE_UPDATER__n0013<8>_xor (PROBABILITY_PROBUPDATE__n0013<8>)
     LUT1_L:I0->LO         1   0.347   0.000  PROBABILITY_PROBUPDATE__n0013<8>_rt (PROBABILITY_PROBUPDATE__n0013<8>_rt)
     MUXCY:S->O            0   0.235   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0011<8>cy (PROBABILITY_PROBUPDATE_UPDATER__n0011<8>_cyo)
     XORCY:CI->O           1   0.824   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0011<9>_xor (PROBABILITY_PROBUPDATE__n0011<9>)
     FDR:D                     0.293          PROBABILITY_PROBUPDATE_NUMERATOR4_9
d839 2
a840 2
    Total                     16.221ns (9.298ns logic, 6.923ns route)
                                       (57.3% logic, 42.7% route)
d844 1
a844 1
  Total number of paths / destination ports: 1938326 / 1222
d846 1
a846 1
Offset:              15.527ns (Levels of Logic = 26)
d848 1
a848 1
  Destination:       PROBABILITY_PROBUPDATE_NUMERATOR4_9 (FF)
d851 1
a851 1
  Data Path: RESET to PROBABILITY_PROBUPDATE_NUMERATOR4_9
d855 1
a855 1
     IBUF:I->O           475   0.653   1.877  RESET_IBUF (RESET_IBUF)
d858 2
a859 2
     LUT4:I2->O            8   0.347   0.653  CONTEXT_BUFFER_Ker01 (CONTEXT_BUFFER_N01)
     LUT4_D:I3->O          6   0.347   0.613  CONTEXT_BUFFER_DATA_OUT<6>_SW0_SW0 (N829)
d861 4
a864 4
     LUT3_L:I2->LO         1   0.347   0.000  PROBABILITY_REFRESH_CONTEXT<4>3 (PROBABILITY_REFRESH_MUX_BLOCK_N4)
     MUXF5:I0->O           1   0.345   0.000  PROBABILITY_REFRESH_CONTEXT<1>_rn_0 (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<1>_MUXF51)
     MUXF6:I0->O           1   0.354   0.000  PROBABILITY_REFRESH_CONTEXT<0> (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<0>_MUXF6)
     MUXF7:I1->O           1   0.354   0.000  PROBABILITY_REFRESH_CONTEXT<2> (PROBABILITY_REFRESH_MUX_BLOCK_CONTEXT<2>_MUXF7)
d866 3
a868 3
     LUT4_D:I1->LO         1   0.347   0.132  PROBABILITY_REFRESH__n0241106 (N969)
     LUT4:I3->O           11   0.347   0.699  PROBABILITY_REFRESH__n0241109_1 (PROBABILITY_REFRESH__n0241109)
     LUT4_D:I2->LO         2   0.347   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0013<0>lut (N979)
d875 5
a879 7
     MUXCY:CI->O           1   0.042   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0013<6>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<6>_cyo)
     MUXCY:CI->O           1   0.042   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0013<7>cy (PROBABILITY_PROBUPDATE_UPDATER__n0013<7>_cyo)
     XORCY:CI->O           2   0.824   0.744  PROBABILITY_PROBUPDATE_UPDATER__n0013<8>_xor (PROBABILITY_PROBUPDATE__n0013<8>)
     LUT1_L:I0->LO         1   0.347   0.000  PROBABILITY_PROBUPDATE__n0013<8>_rt (PROBABILITY_PROBUPDATE__n0013<8>_rt)
     MUXCY:S->O            0   0.235   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0011<8>cy (PROBABILITY_PROBUPDATE_UPDATER__n0011<8>_cyo)
     XORCY:CI->O           1   0.824   0.000  PROBABILITY_PROBUPDATE_UPDATER__n0011<9>_xor (PROBABILITY_PROBUPDATE__n0011<9>)
     FDR:D                     0.293          PROBABILITY_PROBUPDATE_NUMERATOR4_9
d881 2
a882 2
    Total                     15.527ns (8.235ns logic, 7.292ns route)
                                       (53.0% logic, 47.0% route)
d911 1
a911 1
Delay:               7.764ns (Levels of Logic = 4)
d919 1
a919 1
     IBUF:I->O           475   0.653   1.877  RESET_IBUF (RESET_IBUF)
d924 2
a925 2
    Total                      7.764ns (5.090ns logic, 2.674ns route)
                                       (65.6% logic, 34.4% route)
d928 1
a928 1
CPU : 34.83 / 35.22 s | Elapsed : 35.00 / 35.00 s
d932 1
a932 1
Total memory usage is 130364 kilobytes
d935 1
a935 1
Number of warnings :   27 (   0 filtered)
@