head 1.1; branch 1.1.1; access; symbols add:1.1.1.3 update:1.1.1.7 initial:1.1.1.1 samiam95124:1.1.1; locks; strict; comment @# @; 1.1 date 2006.10.06.20.06.52; author samiam95124; state Exp; branches 1.1.1.1; next ; commitid 55f24526b7374567; 1.1.1.1 date 2006.10.06.20.06.52; author samiam95124; state Exp; branches; next 1.1.1.2; commitid 55f24526b7374567; 1.1.1.2 date 2006.10.21.08.40.35; author samiam95124; state Exp; branches; next 1.1.1.3; commitid 72bf4539dcde4567; 1.1.1.3 date 2006.11.01.19.53.00; author samiam95124; state Exp; branches; next 1.1.1.4; commitid 31604548faf04567; 1.1.1.4 date 2006.11.11.11.55.11; author samiam95124; state Exp; branches; next 1.1.1.5; commitid 1fa44555b9f14567; 1.1.1.5 date 2006.11.16.10.19.03; author samiam95124; state Exp; branches; next 1.1.1.6; commitid 3f6c455c3ae54567; 1.1.1.6 date 2006.11.17.10.44.54; author samiam95124; state Exp; branches; next 1.1.1.7; commitid 3e01455d92754567; 1.1.1.7 date 2006.11.19.04.16.14; author samiam95124; state Exp; branches; next ; commitid 3554455fda5a4567; desc @@ 1.1 log @Initial revision @ text @Release 8.2.02i - xst I.33 Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to ./xst/projnav.tmp CPU : 0.00 / 0.23 s | Elapsed : 0.00 / 1.00 s --> Parameter xsthdpdir set to ./xst CPU : 0.00 / 0.23 s | Elapsed : 0.00 / 1.00 s --> Reading design: testbench.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report 9.1) Device utilization summary 9.2) TIMING REPORT ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "testbench.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "testbench" Output Format : NGC Target Device : xc3s200-5-pq208 ---- Source Options Top Module Name : testbench Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto FSM Style : lut RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : YES Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES ROM Style : Auto Mux Extraction : YES Resource Sharing : YES Multiplier Style : auto Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 500 Add Generic Clock Buffer(BUFG) : 8 Register Duplication : YES Slice Packing : YES Pack IO Registers into IOBs : auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : NO RTL Output : Yes Global Optimization : AllClockNets Write Timing Constraints : NO Hierarchy Separator : / Bus Delimiter : <> Case Specifier : maintain Slice Utilization Ratio : 100 Slice Utilization Ratio Delta : 5 ---- Other Options lso : testbench.lso Read Cores : YES cross_clock_analysis : NO verilog2001 : YES safe_implementation : No Optimize Instantiated Primitives : NO use_clock_enable : Yes use_sync_set : Yes use_sync_reset : Yes ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling verilog file "cpu8080.v" in library work Module compiled Compiling verilog file "testbench.v" in library work Module compiled Module compiled Module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Analyzing hierarchy for module in library . Building hierarchy successfully finished. ========================================================================= * HDL Analysis * ========================================================================= Analyzing top module . Module is correct for synthesis. Analyzing module is correct for synthesis. Analyzing module in library . WARNING:Xst:905 - "testbench.v" line 229: The signals are missing in the sensitivity list of always block. Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. Analyzing module in library . Module is correct for synthesis. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit . Related source file is "testbench.v". Found 8-bit tristate buffer for signal . Summary: inferred 8 Tristate(s). Unit synthesized. Synthesizing Unit . Related source file is "testbench.v". Found 1024x8-bit single-port block RAM for signal . ----------------------------------------------------------------------- | ram_style | Auto | | ----------------------------------------------------------------------- | Port A | | aspect ratio | 1024-word x 8-bit | | | mode | read-first | | | clkA | connected to signal | rise | | enA | connected to signal . Related source file is "testbench.v". Found 1-bit register for signal . Found 8-bit tristate buffer for signal . Found 8-bit register for signal . Found 4-bit comparator equal for signal . Found 4-bit register for signal . Summary: inferred 13 D-type flip-flop(s). inferred 1 Comparator(s). inferred 8 Tristate(s). Unit . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block . WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch (without init value) has a constant value of 0 in block