head 1.1; branch 1.1.1; access; symbols add:1.1.1.3 update:1.1.1.3 initial:1.1.1.1 samiam95124:1.1.1; locks; strict; comment @# @; 1.1 date 2006.10.06.20.06.52; author samiam95124; state Exp; branches 1.1.1.1; next ; commitid 55f24526b7374567; 1.1.1.1 date 2006.10.06.20.06.52; author samiam95124; state Exp; branches; next 1.1.1.2; commitid 55f24526b7374567; 1.1.1.2 date 2006.10.21.08.40.35; author samiam95124; state Exp; branches; next 1.1.1.3; commitid 72bf4539dcde4567; 1.1.1.3 date 2006.11.01.19.53.00; author samiam95124; state Exp; branches; next ; commitid 31604548faf04567; desc @@ 1.1 log @Initial revision @ text @//////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995-2003 Xilinx, Inc. // All Right Reserved. //////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version : 8.2.02i // \ \ Application : ISE // / / Filename : cpu_tbw.tfw // /___/ /\ Timestamp : Sat Sep 23 19:23:16 2006 // \ \ / \ // \___\/\___\ // //Command: //Design Name: cpu_tbw //Device: Xilinx // `timescale 1ns/1ps module cpu_tbw; wire [15:0] addr; reg [7:0] data$inout$reg = 8'bZZZZZZZZ; wire [7:0] data = data$inout$reg; wire readmem; wire writemem; wire readio; wire writeio; reg intr = 1'b0; wire inta; reg waitr = 1'b0; reg reset = 1'b1; reg clock = 1'b0; parameter PERIOD = 200; parameter real DUTY_CYCLE = 0.5; parameter OFFSET = 0; initial // Clock process for clock begin #OFFSET; forever begin clock = 1'b0; #(PERIOD-(PERIOD*DUTY_CYCLE)) clock = 1'b1; #(PERIOD*DUTY_CYCLE); end end testbench UUT ( .addr(addr), .data(data), .readmem(readmem), .writemem(writemem), .readio(readio), .writeio(writeio), .intr(intr), .inta(inta), .waitr(waitr), .reset(reset), .clock(clock)); integer TX_FILE = 0; integer TX_ERROR = 0; initial begin // Open the results file... TX_FILE = $fopen("results.txt"); #10200 // Final time: 10200 ns if (TX_ERROR == 0) begin $display("No errors or warnings."); $fdisplay(TX_FILE, "No errors or warnings."); end else begin $display("%d errors found in simulation.", TX_ERROR); $fdisplay(TX_FILE, "%d errors found in simulation.", TX_ERROR); end $fclose(TX_FILE); $stop; end initial begin // ------------- Current Time: 115ns #115; CHECK_inta(1'b0); CHECK_readio(1'b0); CHECK_readmem(1'b0); CHECK_writeio(1'b0); CHECK_writemem(1'b0); // ------------------------------------- // ------------- Current Time: 485ns #370; reset = 1'b0; // ------------------------------------- // ------------- Current Time: 515ns #30; CHECK_readmem(1'b1); CHECK_addr(16'b0000000000000000); // ------------------------------------- // ------------- Current Time: 715ns #200; CHECK_readmem(1'b0); // ------------------------------------- // ------------- Current Time: 915ns #200; CHECK_readmem(1'b1); CHECK_addr(16'b0000000000000001); // ------------------------------------- // ------------- Current Time: 1115ns #200; CHECK_readmem(1'b0); // ------------------------------------- // ------------- Current Time: 1315ns #200; CHECK_readmem(1'b1); CHECK_addr(16'b0000000000000010); // ------------------------------------- // ------------- Current Time: 1515ns #200; CHECK_readmem(1'b0); // ------------------------------------- // ------------- Current Time: 1715ns #200; CHECK_readmem(1'b1); CHECK_addr(16'b0000000000000011); // ------------------------------------- // ------------- Current Time: 1915ns #200; CHECK_readmem(1'b0); // ------------------------------------- // ------------- Current Time: 2315ns #400; CHECK_readmem(1'b1); CHECK_addr(16'b0000000000000000); // ------------------------------------- // ------------- Current Time: 2515ns #200; CHECK_readmem(1'b0); // ------------------------------------- // ------------- Current Time: 2715ns #200; CHECK_readmem(1'b1); CHECK_addr(16'b0000000000000001); // ------------------------------------- // ------------- Current Time: 2915ns #200; CHECK_readmem(1'b0); // ------------------------------------- // ------------- Current Time: 3115ns #200; CHECK_readmem(1'b1); CHECK_addr(16'b0000000000000010); // ------------------------------------- // ------------- Current Time: 3315ns #200; CHECK_readmem(1'b0); // ------------------------------------- // ------------- Current Time: 3515ns #200; CHECK_readmem(1'b1); CHECK_addr(16'b0000000000000011); // ------------------------------------- // ------------- Current Time: 3715ns #200; CHECK_readmem(1'b0); // ------------------------------------- // ------------- Current Time: 4115ns #400; CHECK_readmem(1'b1); CHECK_addr(16'b0000000000000000); // ------------------------------------- // ------------- Current Time: 4315ns #200; CHECK_readmem(1'b0); // ------------------------------------- // ------------- Current Time: 4515ns #200; CHECK_readmem(1'b1); CHECK_addr(16'b0000000000000001); // ------------------------------------- // ------------- Current Time: 4715ns #200; CHECK_readmem(1'b0); // ------------------------------------- // ------------- Current Time: 4915ns #200; CHECK_readmem(1'b1); CHECK_addr(16'b0000000000000010); // ------------------------------------- // ------------- Current Time: 5115ns #200; CHECK_readmem(1'b0); // ------------------------------------- // ------------- Current Time: 5315ns #200; CHECK_readmem(1'b1); CHECK_addr(16'b0000000000000011); // ------------------------------------- // ------------- Current Time: 5515ns #200; CHECK_readmem(1'b0); // ------------------------------------- // ------------- Current Time: 5915ns #400; CHECK_readmem(1'b1); CHECK_addr(16'b0000000000000000); // ------------------------------------- // ------------- Current Time: 6115ns #200; CHECK_readmem(1'b0); // ------------------------------------- // ------------- Current Time: 6315ns #200; CHECK_readmem(1'b1); CHECK_addr(16'b0000000000000001); // ------------------------------------- // ------------- Current Time: 6515ns #200; CHECK_readmem(1'b0); // ------------------------------------- // ------------- Current Time: 6715ns #200; CHECK_readmem(1'b1); CHECK_addr(16'b0000000000000010); // ------------------------------------- // ------------- Current Time: 6915ns #200; CHECK_readmem(1'b0); // ------------------------------------- // ------------- Current Time: 7115ns #200; CHECK_readmem(1'b1); CHECK_addr(16'b0000000000000011); // ------------------------------------- // ------------- Current Time: 7315ns #200; CHECK_readmem(1'b0); // ------------------------------------- // ------------- Current Time: 7715ns #400; CHECK_readmem(1'b1); CHECK_addr(16'b0000000000000000); // ------------------------------------- // ------------- Current Time: 7915ns #200; CHECK_readmem(1'b0); // ------------------------------------- // ------------- Current Time: 8115ns #200; CHECK_readmem(1'b1); CHECK_addr(16'b0000000000000001); // ------------------------------------- // ------------- Current Time: 8315ns #200; CHECK_readmem(1'b0); // ------------------------------------- // ------------- Current Time: 8515ns #200; CHECK_readmem(1'b1); CHECK_addr(16'b0000000000000010); // ------------------------------------- // ------------- Current Time: 8715ns #200; CHECK_readmem(1'b0); // ------------------------------------- // ------------- Current Time: 8915ns #200; CHECK_readmem(1'b1); CHECK_addr(16'b0000000000000011); // ------------------------------------- // ------------- Current Time: 9115ns #200; CHECK_readmem(1'b0); // ------------------------------------- // ------------- Current Time: 9515ns #400; CHECK_readmem(1'b1); CHECK_addr(16'b0000000000000000); // ------------------------------------- // ------------- Current Time: 9715ns #200; CHECK_readmem(1'b0); // ------------------------------------- // ------------- Current Time: 9915ns #200; CHECK_readmem(1'b1); CHECK_addr(16'b0000000000000001); // ------------------------------------- end task CHECK_addr; input [15:0] NEXT_addr; #0 begin if (NEXT_addr !== addr) begin $display("Error at time=%dns addr=%b, expected=%b", $time, addr, NEXT_addr); $fdisplay(TX_FILE, "Error at time=%dns addr=%b, expected=%b", $time, addr, NEXT_addr); $fflush(TX_FILE); TX_ERROR = TX_ERROR + 1; end end endtask task CHECK_readmem; input NEXT_readmem; #0 begin if (NEXT_readmem !== readmem) begin $display("Error at time=%dns readmem=%b, expected=%b", $time, readmem, NEXT_readmem); $fdisplay(TX_FILE, "Error at time=%dns readmem=%b, expected=%b", $time, readmem, NEXT_readmem); $fflush(TX_FILE); TX_ERROR = TX_ERROR + 1; end end endtask task CHECK_writemem; input NEXT_writemem; #0 begin if (NEXT_writemem !== writemem) begin $display("Error at time=%dns writemem=%b, expected=%b", $time, writemem, NEXT_writemem); $fdisplay(TX_FILE, "Error at time=%dns writemem=%b, expected=%b", $time, writemem, NEXT_writemem); $fflush(TX_FILE); TX_ERROR = TX_ERROR + 1; end end endtask task CHECK_readio; input NEXT_readio; #0 begin if (NEXT_readio !== readio) begin $display("Error at time=%dns readio=%b, expected=%b", $time, readio, NEXT_readio); $fdisplay(TX_FILE, "Error at time=%dns readio=%b, expected=%b", $time, readio, NEXT_readio); $fflush(TX_FILE); TX_ERROR = TX_ERROR + 1; end end endtask task CHECK_writeio; input NEXT_writeio; #0 begin if (NEXT_writeio !== writeio) begin $display("Error at time=%dns writeio=%b, expected=%b", $time, writeio, NEXT_writeio); $fdisplay(TX_FILE, "Error at time=%dns writeio=%b, expected=%b", $time, writeio, NEXT_writeio); $fflush(TX_FILE); TX_ERROR = TX_ERROR + 1; end end endtask task CHECK_inta; input NEXT_inta; #0 begin if (NEXT_inta !== inta) begin $display("Error at time=%dns inta=%b, expected=%b", $time, inta, NEXT_inta); $fdisplay(TX_FILE, "Error at time=%dns inta=%b, expected=%b", $time, inta, NEXT_inta); $fflush(TX_FILE); TX_ERROR = TX_ERROR + 1; end end endtask endmodule @ 1.1.1.1 log @8080 CPU project @ text @@ 1.1.1.2 log @8080 CPU project @ text @d11 1 a11 1 // /___/ /\ Timestamp : Fri Oct 20 21:19:57 2006 d29 1 a29 1 wire intr; d83 2 a84 1 CHECK_intr(1'bZ); d111 2 a112 2 // ------------- Current Time: 1515ns #400; d116 1 a116 1 // ------------- Current Time: 1715ns d120 1 a120 1 // ------------- Current Time: 1915ns d125 1 a125 1 // ------------- Current Time: 2115ns d129 5 d135 2 a136 2 #400; CHECK_writeio(1'b1); d140 6 a145 1 CHECK_writeio(1'b0); d148 1 a148 1 #400; d150 1 a150 1 CHECK_addr(16'b0000000000000100); d159 1 a159 1 CHECK_addr(16'b0000000000000101); d168 1 a168 1 CHECK_addr(16'b0000000000000110); d177 1 a177 1 CHECK_addr(16'b0000000000000111); d185 1 d190 1 a190 1 CHECK_writeio(1'b1); d194 6 a199 1 CHECK_writeio(1'b0); d201 1 a201 1 // ------------- Current Time: 5715ns d204 1 a204 1 CHECK_addr(16'b0000000000001000); d206 1 a206 1 // ------------- Current Time: 5915ns d210 1 a210 1 // ------------- Current Time: 6115ns d213 1 a213 1 CHECK_addr(16'b0000000000001001); d215 1 a215 1 // ------------- Current Time: 6315ns d220 1 a220 1 #400; d222 1 a222 1 CHECK_addr(16'b0000000000001010); d231 1 a231 1 CHECK_addr(16'b0000000000001011); a236 4 // ------------- Current Time: 7515ns #200; CHECK_addr(16'b0000000000000101); // ------------------------------------- d238 3 a240 2 #200; CHECK_writeio(1'b1); d244 1 a244 1 CHECK_writeio(1'b0); d246 2 a247 2 // ------------- Current Time: 8315ns #400; d249 1 a249 1 CHECK_addr(16'b0000000000001100); d251 1 a251 1 // ------------- Current Time: 8515ns d255 1 a255 1 // ------------- Current Time: 8715ns d258 1 a258 1 CHECK_addr(16'b0000000000001101); d260 1 a260 1 // ------------- Current Time: 8915ns d264 2 a265 2 // ------------- Current Time: 9315ns #400; d267 1 a267 1 CHECK_addr(16'b0000000000001110); d269 1 a269 1 // ------------- Current Time: 9515ns d273 5 d280 1 a280 2 CHECK_readmem(1'b1); CHECK_addr(16'b0000000000001111); d284 2 a285 1 CHECK_readmem(1'b0); a348 12 task CHECK_intr; input NEXT_intr; #0 begin if (NEXT_intr !== intr) begin $display("Error at time=%dns intr=%b, expected=%b", $time, intr, NEXT_intr); $fdisplay(TX_FILE, "Error at time=%dns intr=%b, expected=%b", $time, intr, NEXT_intr); $fflush(TX_FILE); TX_ERROR = TX_ERROR + 1; end end endtask @ 1.1.1.3 log @8080 CPU project @ text @d11 1 a11 1 // /___/ /\ Timestamp : Sat Oct 28 09:12:59 2006 d23 1 a23 1 reg [7:0] data$inout$reg = 8'bZ1Z00000; d32 1 a32 6 wire [2:0] r; wire [2:0] g; wire [2:0] b; wire hsync_n; wire vsync_n; reg reset = 1'b0; a59 5 .r(r), .g(g), .b(b), .hsync_n(hsync_n), .vsync_n(vsync_n), d63 291 a353 144 integer TX_ERROR = 0; initial begin // Open the results file... #100200 // Final time: 100200 ns if (TX_ERROR == 0) begin $display("No errors or warnings."); end else begin $display("%d errors found in simulation.", TX_ERROR); end $stop; end initial begin // ------------- Current Time: 85ns #85; reset = 1'b1; data$inout$reg = 8'bZZZZZZZZ; // ------------------------------------- // ------------- Current Time: 485ns #400; reset = 1'b0; // ------------------------------------- end task CHECK_addr; input [15:0] NEXT_addr; #0 begin if (NEXT_addr !== addr) begin $display("Error at time=%dns addr=%b, expected=%b", $time, addr, NEXT_addr); TX_ERROR = TX_ERROR + 1; end end endtask task CHECK_readmem; input NEXT_readmem; #0 begin if (NEXT_readmem !== readmem) begin $display("Error at time=%dns readmem=%b, expected=%b", $time, readmem, NEXT_readmem); TX_ERROR = TX_ERROR + 1; end end endtask task CHECK_writemem; input NEXT_writemem; #0 begin if (NEXT_writemem !== writemem) begin $display("Error at time=%dns writemem=%b, expected=%b", $time, writemem, NEXT_writemem); TX_ERROR = TX_ERROR + 1; end end endtask task CHECK_readio; input NEXT_readio; #0 begin if (NEXT_readio !== readio) begin $display("Error at time=%dns readio=%b, expected=%b", $time, readio, NEXT_readio); TX_ERROR = TX_ERROR + 1; end end endtask task CHECK_writeio; input NEXT_writeio; #0 begin if (NEXT_writeio !== writeio) begin $display("Error at time=%dns writeio=%b, expected=%b", $time, writeio, NEXT_writeio); TX_ERROR = TX_ERROR + 1; end end endtask task CHECK_intr; input NEXT_intr; #0 begin if (NEXT_intr !== intr) begin $display("Error at time=%dns intr=%b, expected=%b", $time, intr, NEXT_intr); TX_ERROR = TX_ERROR + 1; end end endtask task CHECK_inta; input NEXT_inta; #0 begin if (NEXT_inta !== inta) begin $display("Error at time=%dns inta=%b, expected=%b", $time, inta, NEXT_inta); TX_ERROR = TX_ERROR + 1; end end endtask task CHECK_r; input [2:0] NEXT_r; #0 begin if (NEXT_r !== r) begin $display("Error at time=%dns r=%b, expected=%b", $time, r, NEXT_r); TX_ERROR = TX_ERROR + 1; end end endtask task CHECK_g; input [2:0] NEXT_g; #0 begin if (NEXT_g !== g) begin $display("Error at time=%dns g=%b, expected=%b", $time, g, NEXT_g); TX_ERROR = TX_ERROR + 1; end end endtask task CHECK_b; input [2:0] NEXT_b; #0 begin if (NEXT_b !== b) begin $display("Error at time=%dns b=%b, expected=%b", $time, b, NEXT_b); TX_ERROR = TX_ERROR + 1; end end endtask task CHECK_hsync_n; input NEXT_hsync_n; #0 begin if (NEXT_hsync_n !== hsync_n) begin $display("Error at time=%dns hsync_n=%b, expected=%b", $time, hsync_n, NEXT_hsync_n); TX_ERROR = TX_ERROR + 1; end end endtask task CHECK_vsync_n; input NEXT_vsync_n; #0 begin if (NEXT_vsync_n !== vsync_n) begin $display("Error at time=%dns vsync_n=%b, expected=%b", $time, vsync_n, NEXT_vsync_n); TX_ERROR = TX_ERROR + 1; end end endtask d355 1 a355 1 endmodule @