head 1.3; access; symbols Rev_XLNX_7:1.3 Rev_XLNX_5:1.2 V10:1.1.1.1 GNU:1.1.1; locks; strict; comment @# @; 1.3 date 2005.06.19.10.07.47; author jsauermann; state Exp; branches; next 1.2; commitid 5b9342b543da4567; 1.2 date 2003.10.12.16.50.29; author jsauermann; state Exp; branches; next 1.1; 1.1 date 2003.09.30.17.58.04; author jsauermann; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2003.09.30.17.58.04; author jsauermann; state Exp; branches; next ; desc @@ 1.3 log @Changes for Xilinx Proj. Nav. 7.1.02i @ text @library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM; --use UNISIM.VComponents.all; use work.cpu_pack.ALL; entity opcode_fetch is Port( CLK_I : in std_logic; T2 : in std_logic; CLR : in std_logic; CE : in std_logic; PC_OP : in std_logic_vector( 2 downto 0); JDATA : in std_logic_vector(15 downto 0); RR : in std_logic_vector(15 downto 0); RDATA : in std_logic_vector( 7 downto 0); PC : out std_logic_vector(15 downto 0) ); end opcode_fetch; architecture Behavioral of opcode_fetch is signal LPC : std_logic_vector(15 downto 0); signal LRET : std_logic_vector( 7 downto 0); begin PC <= LPC; process(CLK_I, CLR) begin if (CLR = '1') then LPC <= X"0000"; elsif ((rising_edge(CLK_I) and T2 = '1') and CE = '1' ) then case PC_OP is when PC_NEXT => LPC <= LPC + 1; -- next address when PC_JMP => LPC <= JDATA; -- jump address when PC_RETL => LRET <= RDATA; -- return address L LPC <= LPC + 1; when PC_RETH => LPC <= RDATA & LRET; -- return address H when PC_JPRR => LPC <= RR; when PC_WAIT => when others => LPC <= X"0008"; -- interrupt end case; end if; end process; end Behavioral; @ 1.2 log @Made cpu_engine WISHBONE compliant. (Somebody please validate it). @ text @d36 1 a36 1 process(CLK_I) d38 14 a51 15 if (rising_edge(CLK_I)) then if (CLR = '1') then LPC <= X"0000"; elsif (CE = '1' and T2 = '1') then case PC_OP is when PC_NEXT => LPC <= LPC + 1; -- next address when PC_JMP => LPC <= JDATA; -- jump address when PC_RETL => LRET <= RDATA; -- return address L LPC <= LPC + 1; when PC_RETH => LPC <= RDATA & LRET; -- return address H when PC_JPRR => LPC <= RR; when PC_WAIT => when others => LPC <= X"0008"; -- interrupt end case; end if; d54 1 a54 1 @ 1.1 log @Initial revision @ text @d39 7 a45 7 if (T2 = '1') then if (CLR = '1') then LPC <= X"0000"; elsif (CE = '1') then case PC_OP is when PC_NEXT => LPC <= LPC + 1; -- next address when PC_JMP => LPC <= JDATA; -- jump address when PC_RETL => LRET <= RDATA; -- return address L d47 5 a51 6 when PC_RETH => LPC <= RDATA & LRET; -- return address H when PC_JPRR => LPC <= RR; when PC_WAIT => when others => LPC <= X"0008"; -- interrupt end case; end if; @ 1.1.1.1 log @no message @ text @@