head 1.3; access; symbols V10:1.1.1.1 GNU:1.1.1; locks; strict; comment @# @; expand @b@; 1.3 date 2003.10.12.18.41.20; author jsauermann; state Exp; branches; next 1.2; 1.2 date 2003.10.03.13.23.24; author jsauermann; state Exp; branches; next 1.1; 1.1 date 2003.09.30.17.57.36; author jsauermann; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2003.09.30.17.57.36; author jsauermann; state Exp; branches; next ; desc @@ 1.3 log @Todo removed @ text @%PDF-1.2 %âãÏÓ 10 0 obj << /Length 11 0 R >> stream BT 176.16 703.92 TD 0 0 0 rg /F0 24 Tf 0.0505 Tc -0.0505 Tw (C16 CPU Documentation) Tj -104.16 -44.88 TD /F0 18 Tf 0.12 Tc 0 Tw (1) Tj 56.64 0 TD 0 Tc -0.06 Tw (History \(why it is as it is\)) Tj -50.88 -23.04 TD /F1 12 Tf 0.0632 Tc 0.2518 Tw (In early 2003, I had finished the design of an STM-1/STM-4 framer. The next step foreard was) Tj -5.76 -13.92 TD 0.0941 Tc -0.2274 Tw (extensive testing, but how? Since I was only using 30% of my FPGA \(a Virtex 100E on an Avnet) Tj 0 -14.16 TD 0.057 Tc -0.267 Tw (board\), I thought a microcontroller on the FPGA would be the easiest solution. The plan was sim-) Tj 0 -13.92 TD 0.0608 Tc 0.0192 Tw (ple enough: download a free CPU core, combine it with the STM framer, and that would be it. A) Tj T* 0.08 Tc -0.2171 Tw (weekend or two should suffice. Well, not exactly.) Tj 5.76 -20.16 TD 0.0896 Tc -0.317 Tw (The first try was an open Z80 core. I chose Z80 since I was programming a lot of Z80 assembler) Tj -5.76 -13.92 TD 0.0585 Tc -0.2985 Tw (back in the 70s \(after the Z80, I fell in love with the 68000\). After downloading the core, I figured) Tj 0 -13.92 TD 0.0668 Tc 0.8265 Tw (that it did not fit into my FPGA. After analyzing the situation, I came to the conclusion, that a) Tj 0 -14.16 TD 0.0949 Tc -0.3649 Tw (8080 would probably be small enough. Since I couldn) Tj -2.64 Tc 0 Tw (\222) Tj 0.08 Tc -0.41 Tw (t a suitable core, I wrote one myself, which) Tj 0 -13.92 TD 0.083 Tc -0.4641 Tw (was finished some weekends later. At some point in time - all instructions were working, but I had) Tj T* 0.0576 Tc 1.1424 Tw (not implemented interrupts yet - I thought it was time to look for a C compiler. I had a small) Tj 0 -14.16 TD 0.0717 Tc 1.3683 Tw (loader that would read intel hex records over a serial interface into the FPGA memory. After) Tj 0 -13.92 TD 0.0708 Tc 0.0845 Tw (searching on the web for some time, I learned that most C compilers were requiring a Z80 rather) Tj T* 0.0849 Tc 0.2351 Tw (than a 8080, and the few 8080 compilers I found had some limitations that I didn) Tj -2.64 Tc 0 Tw (\222) Tj 0.0923 Tc 0.2277 Tw (t like. At least) Tj 0 -14.16 TD 0.0662 Tc -0.2033 Tw (the assemblers I found were ok, so I decided to write my own C compiler.) Tj 5.76 -19.92 TD 0.0765 Tc 2.2935 Tw (A few weekends later, it was already mid 2003, The C compiler for the 8080 was ready.) Tj -5.76 -13.92 TD 0.0686 Tc 0.9284 Tw (Although I exercised some care in generating compact code, even small C programs generated) Tj 0 -14.16 TD 0.081 Tc 0.219 Tw (quite some code, and I had only 8kByte of internal FPGA memory left. I analyzed the generated) Tj 0 -13.92 TD 0.0616 Tc 0.0717 Tw (code, and found that the 8080 was not really made for C. For example, ANDing two 16 bit num-) Tj T* 0.0431 Tc -0.1116 Tw (bers would create a lot of instructions, like:) Tj 28.32 -20.16 TD /F0 12 Tf -0.06 Tc 0 Tw (LD) Tj 56.64 0 TD 0.04 Tc -0.16 Tw (A, C) Tj -56.64 -13.92 TD 0 Tc 0 Tw (AND) Tj 56.64 0 TD -0.12 Tw (A, E) Tj -56.64 -13.92 TD -0.06 Tc 0 Tw (LD) Tj 56.64 0 TD 0 Tc -0.12 Tw (E, A) Tj -56.64 -14.16 TD -0.06 Tc 0 Tw (LD) Tj 56.64 0 TD 0.08 Tc -0.2 Tw (A, B) Tj -56.64 -13.92 TD 0 Tc 0 Tw (AND) Tj 56.64 0 TD 0.04 Tc -0.16 Tw (A, D) Tj -56.64 -13.92 TD -0.06 Tc 0 Tw (LD) Tj 56.64 0 TD 0.04 Tc (D,A) Tj -79.2 -20.16 TD /F1 12 Tf 0.069 Tc -0.369 Tw (Even though \(or actually because\) the 8080 had quite a few registers, the compiler had no choice) Tj -5.76 -13.92 TD 0.0369 Tc -0.4369 Tw (but to move operands back and forth between these registers. Contrary to common wisdom I came) Tj 0 -13.92 TD 0.0486 Tc -0.1153 Tw (to the conclusion that a good CPU does not have as many registers as possible, but instead as few) Tj 0 -14.16 TD 0.0839 Tc -0.2839 Tw (registers as possible. The reasons for this is that \(1\) in FPGAs, internal memory is about as fast as) Tj 0 -13.92 TD 0.1096 Tc 0.2744 Tw (registers, and \(2\) for preemptive multitasking \(which I had in mind from the beginning\), a small) Tj T* 0.0638 Tc 1.8402 Tw (number of registers leads to faster context switches, since all registers need to be saved and) Tj 0 -14.16 TD -0.0533 Tc 0 Tw (restored.) Tj 5.76 -19.92 TD 0.0876 Tc -0.3009 Tw (The next step was then to design my own CPU. Since I was no longer bound by existing compil-) Tj -5.76 -13.92 TD 0.0263 Tc 0.1379 Tw (ers or instruction sets, I could design the CPU in order to suit the compiler, rather than to write a) Tj 0 -14.16 TD 0.0296 Tc 0.9171 Tw (compiler that suits a given CPU. The approach I took was to \(1\) take the 8080 backend of my) Tj 0 -13.92 TD 0.0677 Tc 0.2023 Tw (compiler and to rewrite it towards a hypothetical CPU in such a way that most elementary back-) Tj ET endstream endobj 11 0 obj 4815 endobj 4 0 obj << /Type /Page /Parent 5 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 10 0 R >> endobj 13 0 obj << /Length 14 0 R >> stream BT 72 712.08 TD 0 0 0 rg /F1 12 Tf 0.0644 Tc -0.375 Tw (end operations would need a single 8 bit instruction and \(2\) to design that hypothetical CPU in the) Tj 0 -14.16 TD 0.048 Tc 0 Tw (FPGA.) Tj 5.76 -19.92 TD 0.079 Tc -0.415 Tw (The first decision to make was the number of registers really required. Looking at C expressions,) Tj -5.76 -13.92 TD 0.054 Tc 0.6942 Tw (it turns out that in most nodes of the parsing tree generated by the compiler consists of expres-) Tj 0 -14.16 TD 0.0736 Tc 0.2169 Tw (sions with a left and a right argument. Thus I gave the CPU two registers called LL and RR; LL) Tj 0 -13.92 TD 0.0439 Tc -0.4392 Tw (holds the left argument of a binary operator, RR the right argument, and the result would be stored) Tj T* 0.0972 Tc 0.6934 Tw (in back in RR. For function calls and local variables, a stack pointer, SP, would be required as) Tj 0 -14.16 TD 0.0697 Tc -0.224 Tw (well. This leads to only three registers LL, RR, and SP. and that is enough.) Tj 5.76 -19.92 TD 0.053 Tc -0.069 Tw (The next question is that of addressing modes required. Another common wisdom is that a good) Tj -5.76 -13.92 TD 0.0439 Tc 0.4079 Tw (instruction set is orthogonal, and this turns out to be as wrong as the believe that many registers) Tj 0 -14.16 TD 0.079 Tc 0.116 Tw (are good. In fact, what the compiler really needs is suffucient addressing modes for the leaves of) Tj 0 -13.92 TD 0.0723 Tc 0.1997 Tw (the parse tree \(which are always constants and variables\). Thus the instruction set should be rich) Tj T* 0.066 Tc 2.0571 Tw (in immediated addressing \(e.g. for ++, --, and frequently used binary operators\), SP relative) Tj 0 -14.16 TD 0.0819 Tc 0.0927 Tw (addressing including pre-decrement and post increment for local variables, and absolute address-) Tj 0 -13.92 TD 0.0977 Tc -0.012 Tw (ing for global variables. Orthogonality is not required for these addressing modes, it is suffucient) Tj T* 0.0889 Tc -0.3289 Tw (to have immediate addressing for the RR register only for most binary C operands, while absolute) Tj 0 -14.16 TD 0.0993 Tc -0.1993 Tw (addressing helps also for LL register if a variable is a left operand.) Tj 5.76 -19.92 TD 0.0741 Tc -0.3541 Tw (Another thing to get rid of was a flag register. Considering that in C you can have constructs like) Tj 22.56 -19.92 TD /F0 12 Tf 0.0171 Tc -0.0571 Tw (if \(x > y\)) Tj 113.52 0 TD /F1 12 Tf 0.18 Tc -0.42 Tw (as well as) Tj -113.52 -20.16 TD /F0 12 Tf -0.0343 Tc 0.1543 Tw (z = \(x > y\)) Tj -22.56 -19.92 TD /F1 12 Tf 0.04 Tc 0.5 Tw (it makes more sense to have an opcode for a binary operator ) Tj -2.64 Tc 0 Tw (\221) Tj 0 Tc (>) Tj -2.64 Tc 3.12 Tw (\222 ) Tj -0.01 Tc 0.61 Tw (rather than a compare opcode) Tj -5.76 -13.92 TD 0.0259 Tc 0.4301 Tw (CMP, which sets a flag that needs to be checked later on. The good old 68000 had such a set of) Tj 0 -14.16 TD 0.03 Tc -0.0833 Tw (opcodes \(Scc - set according to condition cc\). Thus the decision was to provide a rich set of com-) Tj 0 -13.92 TD 0.0896 Tc -0.0096 Tw (parison operators and only a limited number of conditional brances \(JMP RRZ and JMP RRNZ -) Tj T* 0.0881 Tc 0.1119 Tw (jump in RR is zero resp. non-zero\) instead of a single compare instruction and a rich set of jump) Tj 0 -14.16 TD 0.0538 Tc -0.1411 Tw (instructions. As a consequence, there is no flag register in our CPU.) Tj 5.76 -19.92 TD 0.0557 Tc 0.7751 Tw (The CPU operastes on 16 bit quantities only; concersion to and from ) Tj 348.24 0 TD /F0 12 Tf -0.06 Tc 0 Tw (char) Tj 23.52 0 TD /F1 12 Tf 0.1108 Tc 0.8492 Tw ( is made when the) Tj -377.52 -13.92 TD 0.0218 Tc 0.2182 Tw (operands are moved into or out of the RR and LL registers \(rather than having the same opcodes) Tj 0 -14.16 TD 0.0733 Tc 0.6467 Tw (for different sizes as with the 68000\), and ) Tj 210.24 0 TD /F0 12 Tf 0 Tc 0 Tw (long) Tj 22.08 0 TD /F1 12 Tf 0.012 Tc 0.738 Tw ( is not supported. The reason for not supporting) Tj -232.32 -13.92 TD /F0 12 Tf -0.06 Tc 0 Tw (long) Tj 22.08 0 TD /F1 12 Tf 0.081 Tc -0.321 Tw ( is essentially FPGA size. A byte operand move into a register is either zero extended or sign) Tj -22.08 -13.92 TD 0.0425 Tc 0.0563 Tw (extended, as dictated by the opcode. In the assembler, we use the notation RU \(R unsigned\) for a) Tj 0 -14.16 TD 0.0523 Tc 0.3289 Tw (byte operand that is zero extended, RS \(R signed\) for a byte operand that is sign extendedm and) Tj 0 -13.92 TD 0.0343 Tc -0.1371 Tw (RR for a word operand. Likewise LU, LS, and LL for the left operand register.) Tj 5.76 -19.92 TD 0.0584 Tc 0.7816 Tw (Most immediate operannd and SP offsets can be short \(8 bit wide\) or long \(16 bit wide\) as to) Tj -5.76 -14.16 TD 0.0457 Tc -0.2057 Tw (reduce the program size.) Tj 0 -36 TD /F0 18 Tf 0.12 Tc 0 Tw (2) Tj 56.64 0 TD -0.03 Tc (Installation) Tj -50.88 -23.04 TD /F1 12 Tf 0.1108 Tc -0.3084 Tw (The CPU comes with an assembler, a C compiler, a simulator, and a few simple utilities for gen-) Tj -5.76 -13.92 TD 0.105 Tc -0.21 Tw (erating vhdl files for the internal memory of the FPGA, communicating with serial ports on a PC,) Tj 0 -13.92 TD 0.0454 Tc 0.2696 Tw (and so on. Everything has been tested on Windows XP, but should also work on other Windows) Tj ET endstream endobj 14 0 obj 5361 endobj 12 0 obj << /Type /Page /Parent 5 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 13 0 R >> endobj 16 0 obj << /Length 17 0 R >> stream BT 72 712.08 TD 0 0 0 rg /F1 12 Tf 0.1037 Tc -0.0472 Tw (versions as well as Linux. I personally prefer Linux, but the fact that my Xilinx tools work under) Tj 0 -14.16 TD 0.0703 Tc -0.1903 Tw (Windows has kind of forced me to do the entire development on Windows.) Tj 0 -29.28 TD /F0 13.92 Tf -0.04 Tc 0 Tw (2.1) Tj 56.64 0 TD 0.0513 Tc (Prerequisites) Tj -50.88 -18.72 TD /F1 12 Tf 0.0576 Tc -0.1605 Tw (For Windows XP, you can use the ) Tj 167.04 0 TD /F0 12 Tf 0.03 Tc 0 Tw (.exe) Tj 19.68 0 TD /F1 12 Tf 0.1371 Tc -0.2571 Tw ( files provided.) Tj -186.72 -19.92 TD 0.06 Tc -0.2446 Tw (For other Windows versions, the tools provided may or may not work without recompilation.) Tj 0 -19.92 TD 0.0655 Tc -0.2026 Tw (For Linux you need to compile the tools.) Tj 0 -20.16 TD 0.1108 Tc -0.3165 Tw (When compilation is required, you should have ) Tj 229.68 0 TD /F0 12 Tf 0.048 Tc 0 Tw (gmake) Tj 33.84 0 TD /F1 12 Tf -0.24 Tc 0.24 Tw (, ) Tj 6 0 TD /F0 12 Tf 0.08 Tc 0 Tw (gcc) Tj 16.56 0 TD /F1 12 Tf -0.24 Tc 0.24 Tw (, ) Tj 5.76 0 TD /F0 12 Tf -0.024 Tc 0 Tw (bison) Tj 27.36 0 TD /F1 12 Tf 0.06 Tc -0.18 Tw (, and ) Tj 26.16 0 TD /F0 12 Tf -0.12 Tc 0 Tw (flex) Tj 18.72 0 TD /F1 12 Tf 0.1067 Tc -0.3467 Tw (. The following sites) Tj -369.84 -13.92 TD 0.042 Tc -0.1106 Tw (are useful for getting these tools for Windows:) Tj 56.64 -40.08 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD 0.0554 Tc (www.mingw.org) Tj 113.52 0 TD 0 Tc (\(gcc\)) Tj -170.16 -13.92 TD -2.64 Tc (\225) Tj 56.64 0 TD -0.0218 Tc (www.gnu.org) Tj 113.52 0 TD 0.1067 Tc -0.1067 Tw (\(gmake, bison, flex\)) Tj -221.04 -34.08 TD 0.12 Tc -0.2 Tw (Even if you don) Tj -2.64 Tc 0 Tw (\222) Tj 0.09 Tc -0.234 Tw (t compile, I would recommend ) Tj 231.36 0 TD /F0 12 Tf 0 Tc 0 Tw (gmake) Tj 34.08 0 TD /F1 12 Tf 0.08 Tc -0.2 Tw ( and ) Tj 23.28 0 TD /F0 12 Tf 0 Tc 0 Tw (gcc) Tj 16.56 0 TD /F1 12 Tf 0.0662 Tc -0.1862 Tw ( at least. Our compiler does little) Tj -311.04 -13.92 TD 0.1003 Tc 0.3797 Tw (type checking, so you should syntax-check your own files with gcc before running the compiler) Tj 0 -13.92 TD 0.0267 Tc 0 Tw (provided.) Tj 0 -29.52 TD /F0 13.92 Tf -0.04 Tc (2.2) Tj 56.64 0 TD 0.0664 Tc -0.1864 Tw (Directory Structure) Tj -50.88 -18.48 TD /F1 12 Tf 0.065 Tc -0.145 Tw (The entire package contains the following directories:) Tj 50.88 -40.08 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf 0.04 Tc (asm) Tj 113.52 0 TD /F1 12 Tf 0.048 Tc -0.168 Tw (source code for the assembler) Tj -170.16 -13.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf 0 Tc (compiler) Tj 113.52 0 TD /F1 12 Tf 0.0384 Tc -0.1344 Tw (source code for the C compiler) Tj -170.16 -14.16 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf 0 Tc (doc) Tj 113.52 0 TD /F1 12 Tf 0.084 Tc -0.204 Tw (contains this document) Tj -170.16 -13.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf 0.08 Tc (memory) Tj 113.52 0 TD /F1 12 Tf 0.016 Tc -0.176 Tw (utility to create ) Tj 74.88 0 TD /F0 12 Tf 0.018 Tc 0 Tw (vhdl/mem_content.vhd) Tj 117.6 0 TD /F1 12 Tf 0.08 Tc -0.56 Tw ( and) Tj 19.92 0 TD /F0 12 Tf 0 Tc -0.36 Tw ( vhdl/) Tj -212.4 -13.92 TD -0.0277 Tc 0 Tw (board_cpu.ucf) Tj 74.16 0 TD /F1 12 Tf 0.1407 Tc -0.2367 Tw ( \(Xilinx and Avnet board specific\)) Tj -244.32 -14.16 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf 0.04 Tc (sim) Tj 113.52 0 TD /F1 12 Tf 0.0288 Tc -0.1488 Tw (source code for the simulator) Tj -170.16 -13.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf -0.06 Tc (vhdl) Tj 113.52 0 TD /F1 12 Tf 0.0424 Tc -0.1624 Tw (vhdl code for the CPU) Tj -226.8 -29.28 TD /F0 13.92 Tf -0.04 Tc 0 Tw (2.3) Tj 56.64 0 TD 0.0196 Tc 0.0524 Tw (Makefiles and Building the Base System) Tj -50.88 -18.72 TD /F1 12 Tf 0.075 Tc -0.235 Tw (There are 3 different targets for the top level Makefile.) Tj 50.88 -40.08 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf -0.04 Tc (loader) Tj 113.52 0 TD /F1 12 Tf 0.0923 Tc -0.2423 Tw (a small program that loads a subsequent memory ) Tj 0 -13.92 TD 0.0825 Tc -0.2196 Tw (image from the serial port of the FPGA.) Tj -170.16 -13.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf 0.03 Tc (test) Tj 113.52 0 TD /F1 12 Tf 0.066 Tc -0.186 Tw (a small monitor program for testing various I/O ) Tj 0 -14.16 TD 0.08 Tc -0.24 Tw (functions of the FPGA) Tj -170.16 -13.92 TD /F0 12 Tf -2.76 Tc 0 Tw (\225) Tj 56.64 0 TD 0 Tc (rtos) Tj 113.52 0 TD /F1 12 Tf 0.0884 Tc -0.2804 Tw (the same monitor as for ) Tj 116.16 0 TD /F0 12 Tf 0.03 Tc 0 Tw (test) Tj 18 0 TD /F1 12 Tf 0.0706 Tc -0.1906 Tw (, but using a preemp-) Tj -134.16 -13.92 TD 0.0852 Tc -0.1652 Tw (tive multitasking operating system) Tj -221.04 -14.16 TD 0.0927 Tc -0.2927 Tw (The anticipated development process is as follows.) Tj 50.88 -19.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD 0.08 Tc -0.24 Tw (Copy the CPU package on your machine) Tj ET endstream endobj 17 0 obj 5059 endobj 15 0 obj << /Type /Page /Parent 5 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 16 0 R >> endobj 19 0 obj << /Length 20 0 R >> stream BT 128.64 712.08 TD 0 0 0 rg /F1 12 Tf -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD 0.1292 Tc -0.3692 Tw (Either install ) Tj 63.84 0 TD /F0 12 Tf 0 Tc 0 Tw (gmake) Tj 34.08 0 TD /F1 12 Tf 0.0545 Tc -0.5825 Tw ( \(recommended\) or else perform the actions in the top ) Tj -97.92 -14.16 TD 0.24 Tc -0.24 Tw (level ) Tj 26.4 0 TD /F0 12 Tf -0.03 Tc 0 Tw (Makefile) Tj 45.36 0 TD /F1 12 Tf 0.135 Tc -0.215 Tw ( manually later on.) Tj -128.4 -13.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD 0.1084 Tc -0.1484 Tw (Build the utilities if required \(see ) Tj 162 0 TD 0.072 Tc -0.168 Tw (2.1 regarding when this is needed\).) Tj -218.64 -13.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD 0.102 Tc -0.27 Tw (If you have a Virtex E evaluation kit from Avnet \() Tj 241.2 0 TD /F0 12 Tf -0.0086 Tc 0 Tw (ADS-XLX-VE-EVL) Tj 102.72 0 TD /F1 12 Tf -0.24 Tc 0.24 Tw (, ) Tj -343.92 -14.16 TD 0.0185 Tc -0.3385 Tw ($150\), then the ) Tj 74.4 0 TD /F0 12 Tf -0.12 Tc 0 Tw (vhdl) Tj 22.56 0 TD /F1 12 Tf 0.0587 Tc -0.495 Tw ( files are ok already. Otherwise, you need to adapt the ) Tj -96.96 -13.92 TD 0.18 Tc -0.24 Tw (top level vhdl file ) Tj 88.08 0 TD /F0 12 Tf -0.02 Tc 0 Tw (vhdl/board_cpu.vhd) Tj 103.68 0 TD /F1 12 Tf 0.1477 Tc -0.2437 Tw ( and the UCF file ) Tj 86.16 0 TD /F0 12 Tf 0 Tc 0 Tw (vhdl/) Tj -277.92 -13.92 TD -0.0277 Tc (board_cpu.ucf) Tj 74.4 0 TD /F1 12 Tf 0.0588 Tc -0.517 Tw ( \(for the Xilinx design flow\) to your actual hardware. Note ) Tj -74.4 -14.16 TD 0.0857 Tc -0.1657 Tw (that the utility ) Tj 70.32 0 TD /F0 12 Tf 0.0514 Tc 0 Tw (memory/makemem) Tj 99.36 0 TD /F1 12 Tf 0.128 Tc -0.308 Tw ( will overwrite the UCF file, so when ) Tj -169.68 -13.92 TD 0.112 Tc -0.24 Tw (you use a different UCF file, then you should use a different name for it, ) Tj 0 -13.92 TD 0.0579 Tc -0.2179 Tw (so that it will not be overwritten,) Tj -56.64 -14.16 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD -0.12 Tc 0.12 Tw (Do ) Tj 17.52 0 TD /F0 12 Tf -0.024 Tc -0.096 Tw (make loader) Tj 63.36 0 TD /F1 12 Tf 0.1029 Tc -0.4329 Tw ( in the top level directory. This compiles ) Tj 195.6 0 TD /F0 12 Tf 0.015 Tc 0 Tw (loader.c) Tj 40.8 0 TD /F1 12 Tf 0 Tc -0.24 Tw ( \(gener-) Tj -317.28 -13.92 TD 0.096 Tc -0.096 Tw (ating ) Tj 27.12 0 TD /F0 12 Tf 0 Tc 0 Tw (loader.asm) Tj 56.16 0 TD /F1 12 Tf 0.1309 Tc -0.1309 Tw (\), assembles ) Tj 61.68 0 TD /F0 12 Tf 0 Tc 0 Tw (loader.asm) Tj 56.4 0 TD /F1 12 Tf 0.1636 Tc -0.3076 Tw ( \(generating a binary file ) Tj -201.36 -13.92 TD /F0 12 Tf -0.012 Tc 0 Tw (loader.bin) Tj 52.32 0 TD /F1 12 Tf 0.192 Tc -0.288 Tw (, an intel hex file ) Tj 84 0 TD /F0 12 Tf -0.036 Tc 0 Tw (loader.ihx) Tj 51.6 0 TD /F1 12 Tf 0.2 Tc -0.296 Tw ( and a list file ) Tj 68.4 0 TD /F0 12 Tf 0.012 Tc 0 Tw (loader.lst) Tj 47.52 0 TD /F1 12 Tf 0 Tc (\), and cre-) Tj -303.84 -14.16 TD (ates ) Tj 21.84 0 TD /F0 12 Tf 0.018 Tc (vhdl/mem_content.vhd) Tj 117.6 0 TD /F1 12 Tf 0.144 Tc -0.204 Tw ( using the utility ) Tj 81.12 0 TD /F0 12 Tf 0.0686 Tc 0 Tw (makemem) Tj 53.28 0 TD /F1 12 Tf 0 Tc (\).) Tj -330.48 -13.92 TD -2.64 Tc (\225) Tj 56.64 0 TD 0.0369 Tc -0.1269 Tw (Compile the VHDL code and download to the FPGA.) Tj -107.52 -34.08 TD 0.0726 Tc 0.1274 Tw (At this point, you should have a working system on a chip. When you connect to the serial port) Tj -5.76 -13.92 TD 0.0273 Tc -0.2407 Tw (of the FPGA \(115,200 kBaud, 8 data bits, no parity, no flow control\) and reset the FPGA, the sys-) Tj 0 -13.92 TD 0.0709 Tc -0.2209 Tw (tem should print the following on the serial output:) Tj 28.32 -20.16 TD /F0 12 Tf -0.048 Tc 0.168 Tw (LOAD >) Tj -22.56 -19.92 TD /F1 12 Tf 0.0911 Tc 0.6571 Tw (This means the system is ready to load the desired application as a series of intel hex records.) Tj -5.76 -13.92 TD 0.0527 Tc -0.4577 Tw (Every intel hex record loaded will be acknowledge by a dot printed on the serial output. Corrupted) Tj 0 -14.16 TD 0.0447 Tc 0.0153 Tw (characters or records are indicated by the message ) Tj 245.28 0 TD /F0 12 Tf -0.03 Tc 0.27 Tw (ERROR: not hex) Tj 88.32 0 TD /F1 12 Tf 0.0923 Tc -0.0123 Tw ( \(invalid character received,) Tj -333.6 -13.92 TD -0.036 Tc -0.012 Tw (check baud rate etc.\) or ) Tj 115.2 0 TD /F0 12 Tf -0.0092 Tc 0.1292 Tw (CHECKSUM ERROR) Tj 116.88 0 TD /F1 12 Tf 0.0646 Tc -0.1246 Tw ( \(rather unlikely to happpen\).) Tj -232.08 -29.28 TD /F0 13.92 Tf -0.04 Tc 0 Tw (2.4) Tj 56.64 0 TD 0.0214 Tc -0.1414 Tw (Building Applications) Tj -50.88 -18.72 TD /F1 12 Tf 0.084 Tc 0.0189 Tw (After the base system containing the loader is working, you can develop your own applications.) Tj -5.76 -13.92 TD 0.0454 Tc -0.114 Tw (Two applications are provided with the CPU: ) Tj 220.8 0 TD /F0 12 Tf 0.03 Tc 0 Tw (test) Tj 18 0 TD /F1 12 Tf 0.16 Tc -0.28 Tw ( and ) Tj 23.28 0 TD /F0 12 Tf 0 Tc 0 Tw (rtos) Tj 20.16 0 TD /F1 12 Tf (.) Tj -276.48 -20.16 TD 0.1029 Tc -0.2229 Tw (To build the application ) Tj 117.84 0 TD /F0 12 Tf 0.03 Tc 0 Tw (test) Tj 18 0 TD /F1 12 Tf 0 Tc -0.12 Tw (, just do) Tj -113.28 -19.92 TD /F0 12 Tf 0.015 Tc 0.105 Tw (make test) Tj -22.56 -19.92 TD /F1 12 Tf 0.048 Tc -0.168 Tw (which creates \(among others\) ) Tj 144.48 0 TD /F0 12 Tf -0.03 Tc 0 Tw (test.ihx) Tj 36.96 0 TD /F1 12 Tf 0.0761 Tc -0.1634 Tw (, which can be loaded into the FPGA via the loader. ) Tj 251.76 0 TD /F0 12 Tf 0.03 Tc 0 Tw (test) Tj 18 0 TD /F1 12 Tf 0.12 Tc -0.12 Tw ( is) Tj -456.96 -14.16 TD 0.1184 Tc 0.9958 Tw (a small monitor that has functions for displaying and modifying memory, setting LEDs on the) Tj 0 -13.92 TD 0.0243 Tc -0.1243 Tw (board, reading the DIP switches on the board, and reading the temperature sensor.) Tj 5.76 -19.92 TD 0.1829 Tc -0.3269 Tw (I was initially using the ) Tj 115.2 0 TD /F0 12 Tf -0.0092 Tc 0 Tw (HyperTerminal) Tj 80.64 0 TD /F1 12 Tf 0.0764 Tc -0.2564 Tw ( program shipped with Windows XP, but copying \(intel) Tj -201.6 -14.16 TD 0.0431 Tc -0.269 Tw (hex\) files to the FPGA was very slow \(even though the baud rate was 115,200\). Therefore I wrote) Tj 0 -13.92 TD 0.0904 Tc 0.081 Tw (the tty.exe program supplied in the package which dumps files much faster on COM1. ) Tj 421.44 0 TD /F0 12 Tf 0 Tc 0 Tw (tty) Tj 13.92 0 TD /F1 12 Tf -0.096 Tc 0.336 Tw ( works) Tj -435.36 -13.92 TD 0.091 Tc -0.091 Tw (from the DOS command line \(program ) Tj 190.56 0 TD /F0 12 Tf 0.08 Tc 0 Tw (cmd) Tj 22.08 0 TD /F1 12 Tf 0.1346 Tc -0.1346 Tw ( in Windows XP\) pretty much like HyperTerminal in) Tj -212.64 -14.16 TD 0.0313 Tc -0.1753 Tw (a window. tty is started as:) Tj 28.32 -19.92 TD /F0 12 Tf 0 Tc 0.12 Tw (tty [filename]) Tj -22.56 -19.92 TD /F1 12 Tf 0.1333 Tc 0.9707 Tw (If no filename is provided, then) Tj 0 Tc 0 Tw ( ) Tj 161.52 0 TD /F0 12 Tf -0.015 Tc (rtos.ihx) Tj 38.88 0 TD /F1 12 Tf 0.1516 Tc 0.8684 Tw ( is assumed by default.) Tj 0 Tc 0 Tw ( ) Tj 118.56 0 TD /F0 12 Tf 0.08 Tc (tty) Tj 14.16 0 TD /F1 12 Tf 0.06 Tc 0.98 Tw ( prints characters received) Tj -338.88 -14.16 TD 0.12 Tc -0.12 Tw (from ) Tj 26.16 0 TD /F0 12 Tf 0.024 Tc 0 Tw (COM1:) Tj 39.36 0 TD /F1 12 Tf 0 Tc -0.16 Tw ( on the ) Tj 35.04 0 TD /F0 12 Tf 0.08 Tc 0 Tw (cmd) Tj 21.84 0 TD /F1 12 Tf 0.1662 Tc -0.4062 Tw ( window in which ) Tj 88.56 0 TD /F0 12 Tf 0 Tc 0 Tw (tty) Tj 13.92 0 TD /F1 12 Tf 0.0229 Tc -0.2895 Tw ( was started and sends characters typed on the key-) Tj ET endstream endobj 20 0 obj 7626 endobj 18 0 obj << /Type /Page /Parent 5 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 19 0 R >> endobj 22 0 obj << /Length 23 0 R >> stream BT 72 712.08 TD 0 0 0 rg /F1 12 Tf -0.0686 Tc -0.0514 Tw (board to ) Tj 42.48 0 TD /F0 12 Tf 0.024 Tc 0 Tw (COM1:) Tj 39.36 0 TD /F1 12 Tf 0.048 Tc -0.108 Tw (. The special character ) Tj 110.88 0 TD /F0 12 Tf -0.06 Tc 0 Tw (^L) Tj 14.88 0 TD /F1 12 Tf 0.08 Tc -0.2 Tw ( causes ) Tj 37.2 0 TD /F0 12 Tf 0 Tc 0 Tw (tty) Tj 13.92 0 TD /F1 12 Tf 0.0554 Tc -0.0954 Tw ( to copy the file ) Tj 81.12 0 TD /F0 12 Tf 0.0133 Tc 0.1067 Tw (filename \() Tj 50.88 0 TD /F1 12 Tf -0.12 Tc 0.12 Tw (or ) Tj 12.96 0 TD /F0 12 Tf -0.015 Tc 0 Tw (rtos.ihx) Tj 39.12 0 TD /F1 12 Tf 0.3 Tc -0.54 Tw ( if no) Tj -442.8 -14.16 TD 0.24 Tc 0 Tw (filename) Tj 42 0 TD /F0 12 Tf 0 Tc 0.12 Tw ( ) Tj 2.88 0 TD /F1 12 Tf 0.0891 Tc -0.1791 Tw (is provided as a command line argument\) to ) Tj 213.84 0 TD /F0 12 Tf 0.024 Tc 0 Tw (COM1:) Tj 39.36 0 TD /F1 12 Tf 0 Tc (.) Tj -298.08 -36 TD /F0 18 Tf 0.12 Tc (3) Tj 56.64 0 TD -0.0189 Tc 0.0789 Tw (Software Description) Tj -56.64 -31.2 TD /F0 13.92 Tf -0.04 Tc 0 Tw (3.1) Tj 56.64 0 TD 0.0512 Tc 0.0688 Tw (C Compiler) Tj -50.88 -18.72 TD /F0 12 Tf -0.0133 Tc 0 Tw (Synopsis:) Tj 79.2 0 TD 0.0207 Tc -0.0507 Tw (cc80 [ -l ] memtop infile [ outfile ]) Tj -79.2 -19.92 TD 0.0267 Tc 0.0933 Tw (Example 1:) Tj 79.2 0 TD 0 Tc 0.06 Tw (cc80 -l 0x2000 loader.c loader.asm) Tj -79.2 -20.16 TD 0.0267 Tc 0.0933 Tw (Example 2:) Tj 79.2 0 TD 0.005 Tc 0.035 Tw (cc80 0x2000 rtos.c rtos.asm) Tj -79.2 -19.92 TD 0.0267 Tc 0 Tw (Function:) Tj 79.2 0 TD /F1 12 Tf 0.1143 Tc 1.3857 Tw (Compile the C source file) Tj 0 Tc 0 Tw ( ) Tj 134.16 0 TD /F0 12 Tf -0.04 Tc (infile) Tj 26.16 0 TD /F1 12 Tf 0.1152 Tc 1.3728 Tw ( and create the assembler file) Tj 0 Tc 0 Tw ( ) Tj 151.92 0 TD /F0 12 Tf -0.0171 Tc (outfile) Tj 32.64 0 TD /F1 12 Tf -0.04 Tc 1.6 Tw (. The -l) Tj -344.88 -13.92 TD 0.0514 Tc -0.0514 Tw (option creates a slightly different startup code intended for a loader, which cop-) Tj 0 -14.16 TD 0.0621 Tc 2.0819 Tw (ies itself to the top of the memory. memtop is the top of the memory \(for) Tj 0 -13.92 TD 0.0662 Tc 0.783 Tw (instance, 0x2000 = 8k for FPGA internal memory, or 0xA000 = 40k when an) Tj T* 0.072 Tc -0.072 Tw (external SRAM is used\).) Tj -79.2 -20.16 TD /F0 12 Tf 0.03 Tc 0 Tw (Limitations:) Tj 79.2 0 TD /F1 12 Tf -0.045 Tc -0.035 Tw (Not too well tested) Tj 0 -19.92 TD -0.0096 Tc -0.0864 Tw (No support for compound \(i.e. ) Tj 149.04 0 TD /F0 12 Tf 0.02 Tc 0 Tw (struct) Tj 30 0 TD /F1 12 Tf 0.0533 Tc -0.0533 Tw (\) function arguments) Tj -179.04 -19.92 TD -0.12 Tc 0.12 Tw (No ) Tj 17.76 0 TD /F0 12 Tf -0.06 Tc 0 Tw (long) Tj 22.08 0 TD /F1 12 Tf -0.03 Tc 0.03 Tw ( data type) Tj -39.84 -20.16 TD 0.0835 Tc -0.2168 Tw (Name should be cc16 \(a left-over from the Z80 compiler\)) Tj -84.96 -29.28 TD /F0 13.92 Tf -0.04 Tc 0 Tw (3.2) Tj 56.64 0 TD 0.0576 Tc (Assembler) Tj -50.88 -18.72 TD /F0 12 Tf -0.0133 Tc (Synopsis:) Tj 79.2 0 TD -0.0115 Tc 0.0515 Tw (assembler infile [ binfile [ listfile[ symfile [ ihxfile ] ] ] ]) Tj -79.2 -19.92 TD 0.03 Tc 0 Tw (Example:) Tj 79.2 0 TD 0.0144 Tc -0.0144 Tw (assembler rtos.asm rtos.bin) Tj -79.2 -19.92 TD 0.0267 Tc 0 Tw (Function:) Tj 79.2 0 TD /F1 12 Tf 0.1366 Tc 0.8418 Tw (Assemble and link the input assembler file and create \(1\) a binary output file) Tj 0 -14.16 TD 0.0978 Tc 0.5879 Tw (\(used by the simulator and by the ) Tj 169.44 0 TD /F0 12 Tf 0.0343 Tc 0 Tw (makemem) Tj 53.28 0 TD /F1 12 Tf 0.1239 Tc 0.699 Tw ( utility\), \(2\) a list file \(useful for) Tj -222.72 -13.92 TD 0.1088 Tc 1.6112 Tw (debugging\), \(3\) a symbol file \(used by the simulator to display source level) Tj 0 -13.92 TD 0.1389 Tc -0.2932 Tw (symbols in a nice way\), and \(4\) an intel hex file \(used by the loader\).) Tj -79.2 -20.16 TD /F0 12 Tf 0 Tc 0 Tw (Limitations) Tj 59.28 0 TD /F1 12 Tf (:) Tj 19.92 0 TD 0.1565 Tc -0.2765 Tw (Can not link several files.) Tj -84.96 -29.28 TD /F0 13.92 Tf -0.04 Tc 0 Tw (3.3) Tj 56.64 0 TD 0.0624 Tc (Simulator) Tj -50.88 -18.72 TD /F0 12 Tf -0.0133 Tc (Synopsis:) Tj 79.2 0 TD -0.0055 Tc 0.0055 Tw (simulate binfile symfile) Tj -79.2 -19.92 TD 0.03 Tc 0 Tw (Example:) Tj 79.2 0 TD 0.015 Tc -0.135 Tw (simulate test.bin test.sym) Tj -79.2 -19.92 TD 0.0267 Tc 0 Tw (Function:) Tj 79.2 0 TD /F1 12 Tf 0.15 Tc -0.15 Tw (Simulate ) Tj 45.84 0 TD /F0 12 Tf -0.0343 Tc 0 Tw (binfile) Tj 32.64 0 TD /F1 12 Tf 0.0884 Tc -0.1684 Tw ( at instruction level.) Tj -157.68 -20.16 TD /F0 12 Tf 0 Tc 0 Tw (Limitations) Tj 59.28 0 TD /F1 12 Tf (:) Tj 19.92 0 TD 0.0768 Tc -0.3168 Tw (Can not simulate interrupts.) Tj -79.2 -19.92 TD /F0 12 Tf 0.0857 Tc 0 Tw (Comment) Tj 50.64 0 TD /F1 12 Tf 0 Tc (:) Tj 28.56 0 TD 0.1075 Tc -0.1293 Tw (The simulator is useful for debugging the compiler and assembler. If something) Tj 0 -13.92 TD 0.0517 Tc 0.7323 Tw (does not work, check if it works in the simulator. If it works in the simulator,) Tj 0 -14.16 TD 0.0494 Tc -0.3044 Tw (then the error is in the hardware \(vhdl\). If it does not work in the simulator, then) Tj 0 -13.92 TD 0.1 Tc -0.292 Tw (the error is in the compiler.) Tj ET endstream endobj 23 0 obj 5301 endobj 21 0 obj << /Type /Page /Parent 5 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 22 0 R >> endobj 25 0 obj << /Length 26 0 R >> stream BT 72 710.64 TD 0 0 0 rg /F0 13.92 Tf -0.04 Tc 0 Tw (3.4) Tj 56.64 0 TD 0.0974 Tc (Makemem) Tj -50.88 -18.72 TD /F0 12 Tf -0.0133 Tc (Synopsis:) Tj 79.2 0 TD 0.0171 Tc 0.1029 Tw (makemem binfile) Tj -79.2 -19.92 TD 0.03 Tc 0 Tw (Example:) Tj 79.2 0 TD 0.0212 Tc 0.0988 Tw (makemem loader.bin) Tj -79.2 -19.92 TD 0.0267 Tc 0 Tw (Function:) Tj 79.2 0 TD /F1 12 Tf 0 Tc (Create ) Tj 34.32 0 TD /F0 12 Tf 0.0052 Tc (../vhdl/mem_content.vhd) Tj 126.96 0 TD /F1 12 Tf 0.18 Tc -0.3 Tw ( from ) Tj 29.28 0 TD /F0 12 Tf -0.0343 Tc 0 Tw (binfile) Tj 32.64 0 TD /F1 12 Tf 0 Tc (.) Tj -302.4 -20.16 TD /F0 12 Tf (Limitations) Tj 59.28 0 TD /F1 12 Tf (:) Tj 19.92 0 TD 0.1239 Tc 0.91 Tw (Output file name should be a command line argument rather than a fixed file) Tj 0 -13.92 TD 0.18 Tc 0 Tw (name) Tj -84.96 -29.28 TD /F0 13.92 Tf -0.04 Tc (3.5) Tj 56.64 0 TD 0 Tc (Tty) Tj -50.88 -18.72 TD /F0 12 Tf -0.0133 Tc (Synopsis:) Tj 79.2 0 TD -0.024 Tc 0.144 Tw (tty ihxfile) Tj -79.2 -19.92 TD 0.03 Tc 0 Tw (Example:) Tj 79.2 0 TD -0.0327 Tc 0.1527 Tw (tty rtos.ihx) Tj -79.2 -20.16 TD 0.0267 Tc 0 Tw (Function:) Tj 79.2 0 TD /F1 12 Tf 0.0893 Tc -0.1579 Tw (Terminal program for Windows. Typing ^L downloads ) Tj 268.08 0 TD /F0 12 Tf -0.0343 Tc 0 Tw (ihxfile) Tj 32.16 0 TD /F1 12 Tf 0 Tc (.) Tj -379.44 -19.92 TD /F0 12 Tf (Limitations) Tj 59.28 0 TD /F1 12 Tf (:) Tj 19.92 0 TD 0.0429 Tc -0.2029 Tw (Baudrate is fixed to 115, 200 Baud) Tj 0 -19.92 TD 0.0267 Tc -0.1139 Tw (Data foirmat fixed to 8 data bits, 1 stop bit, no parity) Tj -84.96 -29.52 TD /F0 13.92 Tf -0.04 Tc 0 Tw (3.6) Tj 56.64 0 TD 0.0368 Tc (Bin2array) Tj -50.88 -18.48 TD /F0 12 Tf -0.0133 Tc (Synopsis:) Tj 79.2 0 TD -0.015 Tc -0.105 Tw (bin2array binfile) Tj -79.2 -20.16 TD 0.03 Tc 0 Tw (Example:) Tj 79.2 0 TD 0.0063 Tc -0.1263 Tw (bin2array loader.bin) Tj -79.2 -19.92 TD 0.0267 Tc 0 Tw (Function:) Tj 79.2 0 TD /F1 12 Tf 0.0761 Tc -0.2132 Tw (Writes a C array respresnting binfile to stdout.) Tj -79.2 -19.92 TD /F0 12 Tf 0.0857 Tc 0 Tw (Comment) Tj 50.64 0 TD /F1 12 Tf 0 Tc (:) Tj 28.56 0 TD 0.0812 Tc 0.2327 Tw (Useful for e.g. providing a loader in an application, so that one application can) Tj 0 -14.16 TD 0.0542 Tc -0.1502 Tw (load another application. See array ) Tj 169.92 0 TD /F0 12 Tf 0.03 Tc 0 Tw (loader[]) Tj 40.56 0 TD /F1 12 Tf 0.08 Tc -0.176 Tw ( in rtos.c for an example.) Tj -295.44 -36 TD /F0 18 Tf 0.12 Tc 0 Tw (4) Tj 56.64 0 TD -0.0095 Tc 0.0695 Tw (Hardware Description) Tj -56.64 -31.2 TD /F0 13.92 Tf -0.04 Tc 0 Tw (4.1) Tj 56.64 0 TD 0.0107 Tc (board_cpu.vhd) Tj -50.88 -18.72 TD /F1 12 Tf 0.1629 Tc -0.3229 Tw (This is the top level design file.) Tj 0 -19.92 TD 0.06 Tc -0.1708 Tw (Adaptations to other boards that the Avnet board should be made in this file.) Tj 0 -20.16 TD 0.1357 Tc -0.2557 Tw (Essentially instantiates ) Tj 112.56 0 TD /F0 12 Tf -0.0133 Tc 0 Tw (cpu16.vhd) Tj 53.04 0 TD /F1 12 Tf 0 Tc (.) Tj -171.36 -29.28 TD /F0 13.92 Tf -0.04 Tc (4.2) Tj 56.64 0 TD 0.0016 Tc (cpu16.vhd) Tj -50.88 -18.72 TD /F1 12 Tf 0.0519 Tc -0.1586 Tw (Breaks down the system on a chip into 3 parts:) Tj 50.88 -19.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf -0.0086 Tc (cpu_engine.vhd) Tj 80.4 0 TD /F1 12 Tf -0.24 Tc 0.24 Tw (. ) Tj 33.12 0 TD 0.1171 Tc -0.5704 Tw (This module is the CPU itself, plus 8kByte onchip ) Tj 0 -13.92 TD 0.12 Tc 0 Tw (RAM.) Tj -170.16 -14.16 TD -2.64 Tc (\225) Tj 56.64 0 TD /F0 12 Tf -0.015 Tc (input_output.vhd) Tj 89.76 0 TD /F1 12 Tf 0 Tc ( ) Tj 23.76 0 TD 0.0821 Tc -0.2021 Tw (This module contains the I/O functions of the ) Tj 0 -13.92 TD 0.0324 Tc -0.1224 Tw (Avnet board. You need to rewrite this module ) Tj T* 0.0726 Tc -0.2326 Tw (\(and possibly the applications\) for other boards.) Tj -170.16 -14.16 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf 0 Tc (bin_to_7segment.vhd) Tj 108.96 0 TD /F1 12 Tf 0.0743 Tc -0.1343 Tw (. This module contains a driver that continuously ) Tj 4.56 -13.92 TD 0.0585 Tc -0.3285 Tw (displays the program counter of the CPU. Usefule ) Tj 0 -13.92 TD 0.091 Tc -0.211 Tw (for debugging the system on a chip.) Tj ET endstream endobj 26 0 obj 4302 endobj 24 0 obj << /Type /Page /Parent 5 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 25 0 R >> endobj 29 0 obj << /Length 30 0 R >> stream BT 72 710.64 TD 0 0 0 rg /F0 13.92 Tf -0.04 Tc 0 Tw (4.3) Tj 56.64 0 TD 0.0298 Tc (bin_to_7segment.vhd) Tj -50.88 -18.72 TD /F1 12 Tf 0.098 Tc 1.2353 Tw (This module samples the PC of the CPU at fixed intervals and shows the value on a pair of) Tj -5.76 -13.92 TD 0.0752 Tc -0.1752 Tw (7segment LEDs. This function is specific to the Avnet board providing the LEDs.) Tj 0 -29.28 TD /F0 13.92 Tf -0.04 Tc 0 Tw (4.4) Tj 56.64 0 TD 0 Tc (input_output.vhd) Tj -50.88 -18.72 TD /F1 12 Tf 0.0658 Tc 1.0142 Tw (This module provids a number of I/O functions that can be accessed by the CPU through the) Tj -5.76 -13.92 TD 0.1029 Tc -0.3429 Tw (assembler instructions) Tj 84.96 -20.16 TD /F0 12 Tf 0.06 Tc 0.06 Tw (IN ) Tj 56.88 0 TD 0.0267 Tc -0.1467 Tw (\(port\), RU) Tj 113.28 0 TD /F1 12 Tf 0.08 Tc 0 Tw (and) Tj -170.16 -19.92 TD /F0 12 Tf -0.04 Tc (OUT) Tj 56.88 0 TD 0.06 Tc -0.18 Tw (R, \(port\)) Tj -136.08 -19.92 TD /F1 12 Tf 0.0835 Tc -0.2435 Tw (The ports implemented are:) Tj 152.16 -52.08 TD -0.04 Tc 0.04 Tw (Port Function) Tj 238.56 0 TD -0.12 Tc 0 Tw (IN) Tj 36 0 TD 0 Tc (OUT) Tj -426.48 -24 TD /F0 12 Tf (IN_RX_DATA) Tj 76.56 0 TD /F1 12 Tf 0.0226 Tc -0.219 Tw (: Data to be transmitted on serial output. In polled operation, ) Tj -76.56 -13.92 TD 0.0514 Tc -0.5314 Tw (you need to check ) Tj 88.08 0 TD /F0 12 Tf -0.0133 Tc 0 Tw (IN_STATUS) Tj 66 0 TD /F1 12 Tf 0.0431 Tc -0.4931 Tw ( before sending data. Reading this port resets ) Tj -154.08 -14.16 TD 0.1309 Tc -0.2269 Tw (bits 4 and 0 in ) Tj 71.04 0 TD /F0 12 Tf 0.0133 Tc 0 Tw (IN_STATUS) Tj 66 0 TD /F1 12 Tf 0 Tc (.) Tj 244.56 28.08 TD (0) Tj -381.6 -49.92 TD /F0 12 Tf -0.0133 Tc (IN_STATUS) Tj 66 0 TD /F1 12 Tf 0.0462 Tc -0.1262 Tw (: Status of serial I/O and timer) Tj -66 -14.16 TD 0.016 Tc -0.196 Tw (Bit 7: not used \(0\)) Tj 0 -13.92 TD 0.0758 Tc -0.2067 Tw (Bit 6: 1 iff timer interrupt enabled and timer interrupt has occured) Tj T* 0.0876 Tc -0.2248 Tw (Bit 5:1 iff serial Tx interrupt enabled and serial Tx is ready to accept data) Tj 0 -14.16 TD 0.1163 Tc -0.227 Tw (Bit 4:1 iff serial Rx interrupt enabled and serial Rx has received valid data) Tj 0 -13.92 TD 0.015 Tc -0.195 Tw (Bit 3: :not used \(0\)) Tj T* 0.08 Tc -0.28 Tw (Bit 2:1 iff timer interrupt has occured) Tj 0 -14.16 TD 0.0754 Tc -0.1654 Tw (Bit 1:iff serial Tx is ready to accept data) Tj 0 -13.92 TD 0.1362 Tc -0.2862 Tw (Bit 0:1 iff serial Rx has received valid data) Tj 381.6 112.08 TD 0 Tc 0 Tw (1) Tj -381.6 -134.16 TD /F0 12 Tf -0.0109 Tc (IN_TEMPERAT) Tj 87.36 0 TD /F1 12 Tf 0.036 Tc -0.126 Tw (: current value from temperature sensor \(8 bit 2) Tj -2.64 Tc 0 Tw (\222) Tj 0.09 Tc -0.09 Tw (s comple-) Tj -87.36 -13.92 TD 0.1054 Tc -0.2254 Tw (ment in degrees Celsius\) \(Avnet board specific\)) Tj 381.6 13.92 TD 0 Tc 0 Tw (2) Tj -381.6 -36 TD /F0 12 Tf (IN_DIP_SWITCH) Tj 95.28 0 TD /F1 12 Tf 0.0528 Tc -0.4261 Tw (: current setting of the DIP switch. \(Avnet board specific\)) Tj 286.32 0 TD 0 Tc 0 Tw (3) Tj -381.6 -21.84 TD /F0 12 Tf -0.0086 Tc (IN_CLK_CTR_LOW) Tj 111.84 0 TD /F1 12 Tf 0.0457 Tc -0.1657 Tw (: current value of a 16 bit clock counter \(low byte\)) Tj 269.76 0 TD 0 Tc 0 Tw (4) Tj -381.6 -22.08 TD /F0 12 Tf (IN_CLK_CTR_HIGH) Tj 115.2 0 TD /F1 12 Tf 0.067 Tc -0.2197 Tw (: current value of a 16 bit clock counter \(high byte\)) Tj 266.4 0 TD 0 Tc 0 Tw (5) Tj -381.6 -22.08 TD /F0 12 Tf -0.0109 Tc (OUT_TX_DATA) Tj 88.56 0 TD /F1 12 Tf 0.07 Tc -0.238 Tw (: Data received on serial input. In polled operation, you ) Tj -88.56 -13.92 TD 0 Tc 0 Tw (need to check ) Tj 68.88 0 TD /F0 12 Tf -0.0133 Tc (IN_STATUS) Tj 66 0 TD /F1 12 Tf 0.054 Tc -0.1607 Tw ( before readiing data. Writing this port resets ) Tj -134.88 -13.92 TD 0.1309 Tc -0.2269 Tw (bits 5 and 1 in ) Tj 71.04 0 TD /F0 12 Tf 0.0133 Tc 0 Tw (IN_STATUS) Tj 66 0 TD /F1 12 Tf 0 Tc (.) Tj 287.04 27.84 TD (0) Tj -424.08 -49.92 TD /F0 12 Tf -0.0343 Tc 0.1543 Tw (not used) Tj 424.08 0 TD /F1 12 Tf 0 Tc 0 Tw (1) Tj -424.08 -22.08 TD /F0 12 Tf -0.015 Tc (OUT_LEDS) Tj 63.36 0 TD /F1 12 Tf 0.0261 Tc -0.1461 Tw (: Turns each of the 8 LEDs on or off. 1 turns LED on.\(Avnet ) Tj -63.36 -13.92 TD 0.1029 Tc -0.3429 Tw (board specific\)) Tj 424.08 13.92 TD 0 Tc 0 Tw (2) Tj ET 71.76 100.32 0.48 419.52 re f 453.36 99.84 0.48 420.48 re f 495.84 99.84 0.48 420.48 re f 537.12 100.32 0.48 419.52 re f 71.76 520.32 m 71.76 519.84 l 537.6 519.84 l 537.6 520.32 l h f 72.24 495.6 m 72.24 495.12 l 537.12 495.12 l 537.12 495.6 l h f 72.24 492.96 m 72.24 492.48 l 537.12 492.48 l 537.12 492.96 l h f 71.76 444.24 m 71.76 443.76 l 537.6 443.76 l 537.6 444.24 l h f 71.76 310.32 m 71.76 309.84 l 537.6 309.84 l 537.6 310.32 l h f 71.76 274.32 m 71.76 273.84 l 537.6 273.84 l 537.6 274.32 l h f 71.76 252.24 m 71.76 251.76 l 537.6 251.76 l 537.6 252.24 l h f 71.76 230.16 m 71.76 229.68 l 537.6 229.68 l 537.6 230.16 l h f 71.76 208.32 m 71.76 207.84 l 537.6 207.84 l 537.6 208.32 l h f 71.76 158.16 m 71.76 157.68 l 537.6 157.68 l 537.6 158.16 l h f 71.76 136.32 m 71.76 135.84 l 537.6 135.84 l 537.6 136.32 l h f 71.76 100.32 m 71.76 99.84 l 537.6 99.84 l 537.6 100.32 l h f endstream endobj 30 0 obj 5365 endobj 27 0 obj << /Type /Page /Parent 28 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 29 0 R >> endobj 32 0 obj << /Length 33 0 R >> stream BT 77.76 502.08 TD 0 0 0 rg /F1 12 Tf 0.0554 Tc 0.0779 Tw (The I/O ports are not in the focus of this document, so please refer to the VHDL files regarding) Tj -5.76 -14.16 TD 0.0829 Tc 0.1571 Tw (theit implementation. You may find the baudrate generator interesting due to its unlimited preci-) Tj 0 -13.92 TD 0.064 Tc -0.204 Tw (sion, and the Rx and Tx parts due to their very low size.) Tj 0 -29.28 TD /F0 13.92 Tf -0.04 Tc 0 Tw (4.5) Tj 56.64 0 TD 0.0141 Tc (cpu_engine.vhd) Tj -50.88 -18.72 TD /F1 12 Tf 0.06 Tc -0.14 Tw (This is the CPU itself. The structure of the ) Tj 206.4 0 TD /F0 12 Tf -0.024 Tc 0 Tw (cpu_engine) Tj 58.08 0 TD /F1 12 Tf 0.14 Tc -0.3 Tw ( is as follows:) Tj -264.48 -244.08 TD 0.0512 Tc 0.9088 Tw (The memory signals are also extended to the outside of this module in order to connect to an) Tj -5.76 -13.92 TD 0.0429 Tc -0.1229 Tw (optional external SRAM and to the ) Tj 171.12 0 TD /F0 12 Tf -0.015 Tc 0 Tw (input_output.vhd) Tj 89.76 0 TD /F1 12 Tf 0.1029 Tc -0.3429 Tw ( module.) Tj -255.12 -19.92 TD 0.3105 Tw (The timing is as follows. All signals are clocked on the rising edge of the 40 MHz input clock.) Tj -5.76 -14.16 TD 0.0759 Tc 0.2241 Tw (However, most signals are clocked on every second clock only. This is controlled by the T2 sig-) Tj 0 -13.92 TD 0.0896 Tc -0.0736 Tw (nal. The internal memory is dual-ported, but only to save address and data multiplexers. The first) Tj T* 0.0429 Tc -0.2429 Tw (clock interval \(say T1, or better ) Tj -2.64 Tc 0 Tw (\221) Tj -0.096 Tc -0.144 Tw (not T2) Tj -2.64 Tc 0 Tw (\222) Tj 0.0511 Tc -0.2474 Tw (\) is used for opcode reads, while the second phase \(T2\) is) Tj 0 -14.16 TD 0.0356 Tc -0.1556 Tw (used for all other \(that is, oprand transfers; immediate operands are counted as opcode reads\).) Tj 6 588 TD /F0 12 Tf 0.02 Tc 0 Tw (OUT_INT_MASK) Tj 95.28 0 TD /F1 12 Tf 0.0587 Tc -0.2114 Tw (: The interrupt maks for Rx, Tx and Timer interrupts. 1 ) Tj -95.28 -13.92 TD 0.1 Tc -0.18 Tw (means interrupt is enabled.) Tj 0 -13.92 TD 0 Tc -0.16 Tw (Bit 7..3: not used) Tj 0 -14.16 TD 0.0821 Tc -0.1621 Tw (Bit 2:Enable Timer interrupt \(1 ms interval\)) Tj 0 -13.92 TD 0.0785 Tc -0.2385 Tw (Bit 1: Enable Rx Interrupt \(receiver has received valid data\)) Tj T* 0.0185 Tc -0.1785 Tw (Bit 0: Enable Tx Interrupt \(transmitter ready to accept data\)) Tj 424.08 69.84 TD 0 Tc 0 Tw (3) Tj -424.08 -91.92 TD /F0 12 Tf -0.024 Tc (OUT_RESET_TIMER) Tj 117.84 0 TD /F1 12 Tf 0.0857 Tc -0.1457 Tw (: Writing clears Timer interrupt) Tj 306.24 0 TD 0 Tc 0 Tw (4) Tj -424.08 -22.08 TD /F0 12 Tf -0.0141 Tc (OUT_START_CLK_CTR) Tj 135.36 0 TD /F1 12 Tf -0.0065 Tc -0.1135 Tw (: Start a 16 bit counter clocked at a rate of 20 ) Tj -135.36 -13.92 TD 0.1111 Tc -0.2611 Tw (MHz. Useful for measuring short intervals with high precision.) Tj 424.08 13.92 TD 0 Tc 0 Tw (5) Tj -424.08 -36 TD /F0 12 Tf -0.0075 Tc (OUT_STOP_CLK_CTR) Tj 126.72 0 TD /F1 12 Tf -0.024 Tc -0.072 Tw (: Stop the 16 bit counter) Tj 25.2 174 TD -0.04 Tc 0.04 Tw (Port Function) Tj 238.56 0 TD -0.12 Tc 0 Tw (IN) Tj 36 0 TD 0 Tc (OUT) Tj ET 71.76 522.24 0.48 197.52 re f 453.36 521.76 0.48 198.48 re f 495.84 521.76 0.48 198.48 re f 537.12 522.24 0.48 197.52 re f 71.76 720.24 m 71.76 719.76 l 537.6 719.76 l 537.6 720.24 l h f 72.24 695.52 m 72.24 695.04 l 537.12 695.04 l 537.12 695.52 l h f 72.24 693.12 m 72.24 692.64 l 537.12 692.64 l 537.12 693.12 l h f 71.76 602.16 m 71.76 601.68 l 537.6 601.68 l 537.6 602.16 l h f 71.76 580.32 m 71.76 579.84 l 537.6 579.84 l 537.6 580.32 l h f 71.76 544.32 m 71.76 543.84 l 537.6 543.84 l 537.6 544.32 l h f 71.76 522.24 m 71.76 521.76 l 537.6 521.76 l 537.6 522.24 l h f 1 1 1 rg 72 217.92 468 184.08 re f 444.72 239.04 84.96 42.48 re f 0 0 0 rg 444.72 279.84 86.64 3.12 re f 528.24 237.36 3.12 44.16 re f 443.28 237.36 86.4 3.12 re f 443.28 239.04 3.12 43.92 re f BT 462 254.88 TD /F0 12 Tf 0.0133 Tc (data_core) Tj ET 1 1 1 rg 260.4 239.04 85.2 42.48 re f 0 0 0 rg 260.4 279.84 86.88 3.12 re f 344.16 237.36 3.12 44.16 re f 258.96 237.36 86.64 3.12 re f 258.96 239.04 3.12 43.92 re f BT 281.76 254.88 TD 0.08 Tc (memory) Tj ET 1 1 1 rg 76.32 239.04 84.96 42.48 re f 0 0 0 rg 76.32 279.84 86.64 3.12 re f 159.84 237.36 3.12 44.16 re f 74.88 237.36 86.4 3.12 re f 74.88 239.04 3.12 43.92 re f BT 85.2 254.88 TD 0.01 Tc (opcode_fetch) Tj ET 1 1 1 rg 253.44 338.16 99.12 42.48 re f 0 0 0 rg 253.44 378.96 100.8 3.12 re f 351.12 336.48 3.12 44.16 re f 252 336.48 100.56 3.12 re f 252 338.16 3.12 43.92 re f BT 261.6 354.24 TD -0.0171 Tc (opcode_decoder) Tj ET 248.88 260.16 m 248.88 263.52 l 249.6 263.28 l 258.96 260.64 l 260.64 260.16 l 258.96 259.68 l 249.6 257.04 l 248.88 256.8 l 248.88 257.52 l 249.36 258 l 258.72 260.64 l 258.96 259.68 l 258.72 259.68 l 249.36 262.32 l 249.6 263.28 l 249.84 262.8 l 249.84 260.16 l h f 248.88 257.52 m 248.88 260.16 l 249.84 260.16 l 249.84 257.52 l h f 249.36 260.16 m 249.36 262.8 l 258.72 260.16 l 249.36 257.52 l h f* 161.04 259.92 0.24 0.48 re f 248.88 259.92 0.24 0.48 re f 161.28 260.4 m 161.28 259.92 l 248.88 259.92 l 248.88 260.4 l h f 357.12 274.32 m 357.12 270.96 l 356.4 271.2 l 347.04 273.84 l 345.36 274.32 l 347.04 274.8 l 356.4 277.68 l 357.12 277.92 l 357.12 277.2 l 356.64 276.72 l 347.28 273.84 l 347.04 274.8 l 347.28 274.8 l 356.64 272.16 l 356.4 271.2 l 356.16 271.68 l 356.16 274.32 l h f 357.12 277.2 m 357.12 274.32 l 356.16 274.32 l 356.16 277.2 l h f 356.64 274.32 m 356.64 271.68 l 347.28 274.32 l 356.64 277.2 l h f* 356.88 274.08 0.24 0.48 re f 444.72 274.08 0.24 0.48 re f 357.12 274.56 m 357.12 274.08 l 444.72 274.08 l 444.72 274.56 l h f 274.56 326.64 m 271.2 326.64 l 271.44 327.36 l 274.08 336.72 l 274.56 338.4 l 275.04 336.72 l 277.68 327.36 l 277.92 326.64 l 277.2 326.64 l 276.72 327.12 l 274.08 336.48 l 275.04 336.72 l 275.04 336.48 l 272.4 327.12 l 271.44 327.36 l 271.92 327.6 l 274.56 327.6 l h f 277.2 326.64 m 274.56 326.64 l 274.56 327.6 l 277.2 327.6 l h f 274.56 327.12 m 271.92 327.12 l 274.56 336.48 l 277.2 327.12 l h f* 274.32 281.52 m 274.32 281.28 l 274.8 281.28 l 274.8 281.52 l h f 274.32 326.64 m 274.32 326.88 l 274.8 326.88 l 274.8 326.64 l h f 274.32 281.52 0.48 45.12 re f 357.12 260.16 m 357.12 256.8 l 356.4 257.04 l 347.04 259.68 l 345.36 260.16 l 347.04 260.64 l 356.4 263.28 l 357.12 263.52 l 357.12 262.8 l 356.64 262.32 l 347.28 259.68 l 347.04 260.64 l 347.28 260.64 l 356.64 258 l 356.4 257.04 l 356.16 257.52 l 356.16 260.16 l h f 357.12 262.8 m 357.12 260.16 l 356.16 260.16 l 356.16 262.8 l h f 356.64 260.16 m 356.64 257.52 l 347.28 260.16 l 356.64 262.8 l h f* 356.88 259.92 0.24 0.48 re f 444.72 259.92 0.24 0.48 re f 357.12 260.4 m 357.12 259.92 l 444.72 259.92 l 444.72 260.4 l h f BT 175.44 262.32 TD /F0 9.84 Tf 0.1056 Tc (PC) Tj 106.56 45.84 TD 0.152 Tc (OPC) Tj ET 487.2 293.04 m 490.56 293.04 l 490.32 292.32 l 487.68 283.2 l 487.2 281.52 l 486.72 283.2 l 484.08 292.32 l 483.84 293.04 l 484.56 293.04 l 485.04 292.56 l 487.68 283.44 l 486.72 283.2 l 486.72 283.44 l 489.36 292.56 l 490.32 292.32 l 489.84 292.08 l 487.2 292.08 l h f 484.56 293.04 m 487.2 293.04 l 487.2 292.08 l 484.56 292.08 l h f 487.2 292.56 m 489.84 292.56 l 487.2 283.44 l 484.56 292.56 l h f* 352.32 359.28 0.24 0.48 re f 356.4 359.28 0.24 0.48 re f 352.56 359.76 m 352.56 359.28 l 356.4 359.28 l 356.4 359.76 l h f 362.4 359.28 0.24 0.48 re f* 369.84 359.28 0.24 0.48 re f* 362.64 359.76 m 362.64 359.28 l 369.84 359.28 l 369.84 359.76 l h f* 375.84 359.28 0.24 0.48 re f* 383.28 359.28 0.24 0.48 re f* 376.08 359.76 m 376.08 359.28 l 383.28 359.28 l 383.28 359.76 l h f* 389.28 359.28 0.24 0.48 re f* 396.72 359.28 0.24 0.48 re f* 389.52 359.76 m 389.52 359.28 l 396.72 359.28 l 396.72 359.76 l h f* 402.72 359.28 0.24 0.48 re f* 410.16 359.28 0.24 0.48 re f* 402.96 359.76 m 402.96 359.28 l 410.16 359.28 l 410.16 359.76 l h f* 416.16 359.28 0.24 0.48 re f* 423.6 359.28 0.24 0.48 re f* 416.4 359.76 m 416.4 359.28 l 423.6 359.28 l 423.6 359.76 l h f* 429.6 359.28 0.24 0.48 re f* 437.04 359.28 0.24 0.48 re f* 429.84 359.76 m 429.84 359.28 l 437.04 359.28 l 437.04 359.76 l h f* 443.04 359.28 0.24 0.48 re f* 450.48 359.28 0.24 0.48 re f* 443.28 359.76 m 443.28 359.28 l 450.48 359.28 l 450.48 359.76 l h f* 456.48 359.28 0.24 0.48 re f* 463.92 359.28 0.24 0.48 re f* 456.72 359.76 m 456.72 359.28 l 463.92 359.28 l 463.92 359.76 l h f* 469.92 359.28 0.24 0.48 re f* 477.36 359.28 0.24 0.48 re f* 470.16 359.76 m 470.16 359.28 l 477.36 359.28 l 477.36 359.76 l h f* 483.36 359.28 0.24 0.48 re f 483.6 359.28 3.84 0.48 re f 487.44 355.68 m 487.44 355.44 l 486.96 355.44 l 486.96 355.68 l h f 486.96 355.68 0.48 3.84 re f 487.44 349.68 m 487.44 349.92 l 486.96 349.92 l 486.96 349.68 l h f* 487.44 342.48 m 487.44 342.24 l 486.96 342.24 l 486.96 342.48 l h f* 486.96 342.48 0.48 7.2 re f* 487.44 336.48 m 487.44 336.72 l 486.96 336.72 l 486.96 336.48 l h f* 487.44 329.28 m 487.44 329.04 l 486.96 329.04 l 486.96 329.28 l h f* 486.96 329.28 0.48 7.2 re f* 487.44 323.28 m 487.44 323.52 l 486.96 323.52 l 486.96 323.28 l h f* 487.44 316.08 m 487.44 315.84 l 486.96 315.84 l 486.96 316.08 l h f* 486.96 316.08 0.48 7.2 re f* 487.44 310.08 m 487.44 310.32 l 486.96 310.32 l 486.96 310.08 l h f* 487.44 302.88 m 487.44 302.64 l 486.96 302.64 l 486.96 302.88 l h f* 486.96 302.88 0.48 7.2 re f* 487.44 296.88 m 487.44 297.12 l 486.96 297.12 l 486.96 296.88 l h f 487.44 293.04 m 487.44 292.8 l 486.96 292.8 l 486.96 293.04 l h f 486.96 293.04 0.48 3.84 re f 118.8 293.04 m 122.16 293.04 l 121.92 292.32 l 119.28 283.2 l 118.8 281.52 l 118.32 283.2 l 115.68 292.32 l 115.44 293.04 l 116.16 293.04 l 116.64 292.56 l 119.28 283.44 l 118.32 283.2 l 118.32 283.44 l 120.96 292.56 l 121.92 292.32 l 121.44 292.08 l 118.8 292.08 l h f 116.16 293.04 m 118.8 293.04 l 118.8 292.08 l 116.16 292.08 l h f 118.8 292.56 m 121.44 292.56 l 118.8 283.44 l 116.16 292.56 l h f* 253.44 352.08 0.24 0.48 re f 249.36 352.08 0.24 0.48 re f 253.44 352.08 m 253.44 352.56 l 249.6 352.56 l 249.6 352.08 l h f 243.36 352.08 0.24 0.48 re f* 235.92 352.08 0.24 0.48 re f* 243.36 352.08 m 243.36 352.56 l 236.16 352.56 l 236.16 352.08 l h f* 229.92 352.08 0.24 0.48 re f* 222.48 352.08 0.24 0.48 re f* 229.92 352.08 m 229.92 352.56 l 222.72 352.56 l 222.72 352.08 l h f* 216.48 352.08 0.24 0.48 re f* 209.04 352.08 0.24 0.48 re f* 216.48 352.08 m 216.48 352.56 l 209.28 352.56 l 209.28 352.08 l h f* 203.04 352.08 0.24 0.48 re f* 195.6 352.08 0.24 0.48 re f* 203.04 352.08 m 203.04 352.56 l 195.84 352.56 l 195.84 352.08 l h f* 189.6 352.08 0.24 0.48 re f* 182.16 352.08 0.24 0.48 re f* 189.6 352.08 m 189.6 352.56 l 182.4 352.56 l 182.4 352.08 l h f* 176.16 352.08 0.24 0.48 re f* 168.72 352.08 0.24 0.48 re f* 176.16 352.08 m 176.16 352.56 l 168.96 352.56 l 168.96 352.08 l h f* 162.72 352.08 0.24 0.48 re f* 155.28 352.08 0.24 0.48 re f* 162.72 352.08 m 162.72 352.56 l 155.52 352.56 l 155.52 352.08 l h f* 149.28 352.08 0.24 0.48 re f* 141.84 352.08 0.24 0.48 re f* 149.28 352.08 m 149.28 352.56 l 142.08 352.56 l 142.08 352.08 l h f* 135.84 352.08 0.24 0.48 re f* 128.4 352.08 0.24 0.48 re f* 135.84 352.08 m 135.84 352.56 l 128.64 352.56 l 128.64 352.08 l h f* 122.4 352.08 0.24 0.48 re f 118.56 352.08 3.84 0.48 re f 119.04 348.72 m 119.04 348.48 l 118.56 348.48 l 118.56 348.72 l h f 118.56 348.72 0.48 3.6 re f 119.04 341.76 m 119.04 342 l 118.56 342 l 118.56 341.76 l h f* 119.04 333.6 m 119.04 333.36 l 118.56 333.36 l 118.56 333.6 l h f* 118.56 333.6 0.48 8.16 re f* 119.04 326.64 m 119.04 326.88 l 118.56 326.88 l 118.56 326.64 l h f* 119.04 318.72 m 119.04 318.48 l 118.56 318.48 l 118.56 318.72 l h f* 118.56 318.72 0.48 7.92 re f* 119.04 311.76 m 119.04 312 l 118.56 312 l 118.56 311.76 l h f* 119.04 303.84 m 119.04 303.6 l 118.56 303.6 l 118.56 303.84 l h f* 118.56 303.84 0.48 7.92 re f* 119.04 296.88 m 119.04 297.12 l 118.56 297.12 l 118.56 296.88 l h f 119.04 293.04 m 119.04 292.8 l 118.56 292.8 l 118.56 293.04 l h f 118.56 293.04 0.48 3.84 re f 324.24 293.04 m 327.6 293.04 l 327.36 292.32 l 324.72 283.2 l 324.24 281.52 l 323.76 283.2 l 321.12 292.32 l 320.88 293.04 l 321.6 293.04 l 322.08 292.56 l 324.72 283.44 l 323.76 283.2 l 323.76 283.44 l 326.4 292.56 l 327.36 292.32 l 326.88 292.08 l 324.24 292.08 l h f 321.6 293.04 m 324.24 293.04 l 324.24 292.08 l 321.6 292.08 l h f 324.24 292.56 m 326.88 292.56 l 324.24 283.44 l 321.6 292.56 l h f* 324.48 338.16 m 324.48 338.4 l 324 338.4 l 324 338.16 l h f 324.48 334.56 m 324.48 334.32 l 324 334.32 l 324 334.56 l h f 324 334.56 0.48 3.6 re f 324.48 327.36 m 324.48 327.6 l 324 327.6 l 324 327.36 l h f* 324.48 319.2 m 324.48 318.96 l 324 318.96 l 324 319.2 l h f* 324 319.2 0.48 8.16 re f* 324.48 312 m 324.48 312.24 l 324 312.24 l 324 312 l h f* 324.48 303.84 m 324.48 303.6 l 324 303.6 l 324 303.84 l h f* 324 303.84 0.48 8.16 re f* 324.48 296.88 m 324.48 297.12 l 324 297.12 l 324 296.88 l h f 324.48 293.04 m 324.48 292.8 l 324 292.8 l 324 293.04 l h f 324 293.04 0.48 3.84 re f BT 118.8 354.48 TD 0.0871 Tc (CONTROL) Tj 318 7.2 TD (CONTROL) Tj -105.36 -46.56 TD (CONTROL) Tj 56.64 -38.64 TD 0.1152 Tc (ADR) Tj -14.16 -28.32 TD 0.1182 Tc (RDAT) Tj ET 433.2 246 m 433.2 249.36 l 433.92 249.12 l 443.04 246.48 l 444.72 246 l 443.04 245.52 l 433.92 242.88 l 433.2 242.64 l 433.2 243.36 l 433.68 243.84 l 442.8 246.48 l 443.04 245.52 l 442.8 245.52 l 433.68 248.16 l 433.92 249.12 l 434.16 248.64 l 434.16 246 l h f 433.2 243.36 m 433.2 246 l 434.16 246 l 434.16 243.36 l h f 433.68 246 m 433.68 248.64 l 442.8 246 l 433.68 243.36 l h f* 345.36 245.76 0.24 0.48 re f 433.2 245.76 0.24 0.48 re f 345.6 246.24 m 345.6 245.76 l 433.2 245.76 l 433.2 246.24 l h f BT 388.08 262.32 TD 0.0294 Tc (WDAT) Tj ET 239.04 373.68 m 239.04 377.76 l 239.76 377.52 l 251.76 374.16 l 253.44 373.68 l 251.76 373.2 l 239.76 369.6 l 239.04 369.36 l 239.04 370.08 l 239.52 370.56 l 251.52 374.16 l 251.76 373.2 l 251.52 373.2 l 239.52 376.56 l 239.76 377.52 l 240 377.04 l 240 373.68 l h f 239.04 370.08 m 239.04 373.68 l 240 373.68 l 240 370.08 l h f 239.52 373.68 m 239.52 377.04 l 251.52 373.68 l 239.52 370.08 l h f* 217.44 373.2 0.48 0.96 re f 239.04 373.2 0.48 0.96 re f 217.92 374.16 m 217.92 373.2 l 239.04 373.2 l 239.04 374.16 l h f BT 193.2 369.12 TD 0.0816 Tc (INT) Tj ET endstream endobj 33 0 obj 14915 endobj 31 0 obj << /Type /Page /Parent 28 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 32 0 R >> endobj 35 0 obj << /Length 36 0 R >> stream BT 77.76 500.88 TD 0 0 0 rg /F1 12 Tf 0.1103 Tc -0.1103 Tw (We call a full T2 cycle an M cycle; most opcodes use only a single M cycle \(M1\), opcodes with) Tj -5.76 -13.92 TD 0.0448 Tc 0.1387 Tw (a short immediate operand require two M cycles \(M1 and M2\), and so on. The longest opcode is) Tj 0 -14.16 TD 0.0632 Tc -0.3663 Tw (RET, reading the return address in M2 and M3, plus 2 M cycles delay from the PC to the excution) Tj 0 -13.92 TD 0.096 Tc 0 Tw (unit.) Tj 5.76 -19.92 TD 0.0185 Tc -0.1385 Tw (... documentation ongoing ...) Tj -5.76 -36 TD /F0 18 Tf 0.12 Tc 0 Tw (5) Tj 56.64 0 TD 0.0327 Tc -0.2127 Tw (Future Plans) Tj -50.88 -23.04 TD /F1 12 Tf 0.0417 Tc -0.0417 Tw (Handling trouble reports.) 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693.6 l 423.12 672.24 l 423.6 672.48 l h f 423.12 672.24 0.24 0.48 re f 423.36 672.72 m 444.72 672.72 l 444.96 672.24 l 444.48 672.48 l 451.68 693.84 l 451.68 694.08 l 451.92 694.08 l 452.16 693.6 l 444.96 672.24 l 423.36 672.24 l h f 451.92 694.08 m 473.28 694.08 l 473.28 693.84 l 473.04 693.6 l 451.92 693.6 l h f 480.48 672.48 m 480.48 672.24 l 480 672 l 480 672.24 l h f 473.28 693.84 m 472.8 693.6 l 480 672.24 l 480.48 672.48 l h f 480 672.24 0.24 0.48 re f 480.24 672.72 m 501.36 672.72 l 501.6 672.24 l 501.12 672.48 l 508.32 693.84 l 508.32 694.08 l 508.56 694.08 l 508.8 693.6 l 501.6 672.24 l 480.24 672.24 l h f 508.56 694.08 m 529.92 694.08 l 529.92 693.84 l 529.68 693.6 l 508.56 693.6 l h f 537.12 672.48 m 537.12 672.24 l 536.64 672 l 536.64 672.24 l h f 529.92 693.84 m 529.44 693.6 l 536.64 672.24 l 537.12 672.48 l h f BT 83.28 677.76 TD /F0 9.84 Tf 0.1952 Tc 0 Tw (CLK) Tj ET 168.72 693.84 m 168.72 694.32 l 167.76 694.32 l 167.76 693.84 l h f 168.72 559.2 m 168.72 558.72 l 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684 m 452.4 684.48 l 451.44 684.48 l 451.44 684 l h f* 452.4 677.52 m 452.4 677.04 l 451.44 677.04 l 451.44 677.52 l h f* 451.44 677.52 0.96 6.48 re f* 452.4 671.04 m 452.4 671.52 l 451.44 671.52 l 451.44 671.04 l h f* 452.4 664.56 m 452.4 664.08 l 451.44 664.08 l 451.44 664.56 l h f* 451.44 664.56 0.96 6.48 re f* 452.4 658.08 m 452.4 658.56 l 451.44 658.56 l 451.44 658.08 l h f* 452.4 651.6 m 452.4 651.12 l 451.44 651.12 l 451.44 651.6 l h f* 451.44 651.6 0.96 6.48 re f* 452.4 645.12 m 452.4 645.6 l 451.44 645.6 l 451.44 645.12 l h f* 452.4 638.64 m 452.4 638.16 l 451.44 638.16 l 451.44 638.64 l h f* 451.44 638.64 0.96 6.48 re f* 452.4 632.4 m 452.4 632.88 l 451.44 632.88 l 451.44 632.4 l h f* 452.4 625.92 m 452.4 625.44 l 451.44 625.44 l 451.44 625.92 l h f* 451.44 625.92 0.96 6.48 re f* 452.4 619.44 m 452.4 619.92 l 451.44 619.92 l 451.44 619.44 l h f 452.4 615.84 m 452.4 615.36 l 451.44 615.36 l 451.44 615.84 l h f 451.44 615.84 0.96 3.6 re f 139.68 643.92 0.24 0.48 re f 139.92 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The next step forward was) Tj -5.76 -13.92 TD 0.0941 Tc -0.2274 Tw (extensive testing, but how? Since I was only using 30% of my FPGA \(a Virtex 100E on an Avnet) Tj 0 -14.16 TD 0.054 Tc -0.4211 Tw (board\), I thought a micro controller on the FPGA would be the easiest solution. The plan was sim-) Tj 0 -13.92 TD 0.0608 Tc 0.0192 Tw (ple enough: download a free CPU core, combine it with the STM framer, and that would be it. A) Tj T* 0.08 Tc -0.2171 Tw (weekend or two should suffice. Well, not exactly.) Tj 5.76 -20.16 TD 0.0896 Tc -0.317 Tw (The first try was an open Z80 core. I chose Z80 since I was programming a lot of Z80 assembler) Tj -5.76 -13.92 TD 0.0585 Tc -0.2985 Tw (back in the 70s \(after the Z80, I fell in love with the 68000\). After downloading the core, I figured) Tj 0 -13.92 TD 0.0668 Tc 0.8265 Tw (that it did not fit into my FPGA. After analyzing the situation, I came to the conclusion, that a) Tj 0 -14.16 TD 0.0949 Tc -0.3649 Tw (8080 would probably be small enough. Since I couldn) Tj -2.64 Tc 0 Tw (\222) Tj 0.08 Tc -0.41 Tw (t a suitable core, I wrote one myself, which) Tj 0 -13.92 TD 0.083 Tc -0.4641 Tw (was finished some weekends later. At some point in time - all instructions were working, but I had) Tj T* 0.0576 Tc 1.1424 Tw (not implemented interrupts yet - I thought it was time to look for a C compiler. I had a small) Tj 0 -14.16 TD 0.0717 Tc 1.3683 Tw (loader that would read intel hex records over a serial interface into the FPGA memory. After) Tj 0 -13.92 TD 0.0708 Tc 0.0845 Tw (searching on the web for some time, I learned that most C compilers were requiring a Z80 rather) Tj T* 0.0849 Tc 0.2351 Tw (than a 8080, and the few 8080 compilers I found had some limitations that I didn) Tj -2.64 Tc 0 Tw (\222) Tj 0.0923 Tc 0.2277 Tw (t like. At least) Tj 0 -14.16 TD 0.0662 Tc -0.2033 Tw (the assemblers I found were ok, so I decided to write my own C compiler.) Tj 5.76 -19.92 TD 0.0765 Tc 2.2935 Tw (A few weekends later, it was already mid 2003, The C compiler for the 8080 was ready.) Tj -5.76 -13.92 TD 0.0686 Tc 0.9284 Tw (Although I exercised some care in generating compact code, even small C programs generated) Tj 0 -14.16 TD 0.081 Tc 0.219 Tw (quite some code, and I had only 8kByte of internal FPGA memory left. I analyzed the generated) Tj 0 -13.92 TD 0.0616 Tc 0.0717 Tw (code, and found that the 8080 was not really made for C. For example, ANDing two 16 bit num-) Tj T* 0.0431 Tc -0.1116 Tw (bers would create a lot of instructions, like:) Tj 28.32 -20.16 TD /F0 12 Tf -0.06 Tc 0 Tw (LD) Tj 56.64 0 TD 0.04 Tc -0.16 Tw (A, C) Tj -56.64 -13.92 TD 0 Tc 0 Tw (AND) Tj 56.64 0 TD -0.12 Tw (A, E) Tj -56.64 -13.92 TD -0.06 Tc 0 Tw (LD) Tj 56.64 0 TD 0 Tc -0.12 Tw (E, A) Tj -56.64 -14.16 TD -0.06 Tc 0 Tw (LD) Tj 56.64 0 TD 0.08 Tc -0.2 Tw (A, B) Tj -56.64 -13.92 TD 0 Tc 0 Tw (AND) Tj 56.64 0 TD 0.04 Tc -0.16 Tw (A, D) Tj -56.64 -13.92 TD -0.06 Tc 0 Tw (LD) Tj 56.64 0 TD 0.04 Tc (D,A) Tj -79.2 -20.16 TD /F1 12 Tf 0.069 Tc -0.369 Tw (Even though \(or actually because\) the 8080 had quite a few registers, the compiler had no choice) Tj -5.76 -13.92 TD 0.0369 Tc -0.4369 Tw (but to move operands back and forth between these registers. Contrary to common wisdom I came) Tj 0 -13.92 TD 0.0486 Tc -0.1153 Tw (to the conclusion that a good CPU does not have as many registers as possible, but instead as few) Tj 0 -14.16 TD 0.0839 Tc -0.2839 Tw (registers as possible. The reasons for this is that \(1\) in FPGAs, internal memory is about as fast as) Tj 0 -13.92 TD 0.1096 Tc 0.2744 Tw (registers, and \(2\) for preemptive multitasking \(which I had in mind from the beginning\), a small) Tj T* 0.0638 Tc 1.8402 Tw (number of registers leads to faster context switches, since all registers need to be saved and) Tj 0 -14.16 TD -0.0533 Tc 0 Tw (restored.) Tj 5.76 -19.92 TD 0.0876 Tc -0.3009 Tw (The next step was then to design my own CPU. Since I was no longer bound by existing compil-) Tj -5.76 -13.92 TD 0.0263 Tc 0.1379 Tw (ers or instruction sets, I could design the CPU in order to suit the compiler, rather than to write a) Tj 0 -14.16 TD 0.0296 Tc 0.9171 Tw (compiler that suits a given CPU. The approach I took was to \(1\) take the 8080 backend of my) Tj 0 -13.92 TD 0.0677 Tc 0.2023 Tw (compiler and to rewrite it towards a hypothetical CPU in such a way that most elementary back-) Tj ET endstream endobj 11 0 obj 4817 endobj 4 0 obj << /Type /Page /Parent 5 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 10 0 R >> endobj 13 0 obj << /Length 14 0 R >> stream BT 72 712.08 TD 0 0 0 rg /F1 12 Tf 0.0644 Tc -0.375 Tw (end operations would need a single 8 bit instruction and \(2\) to design that hypothetical CPU in the) Tj 0 -14.16 TD 0.048 Tc 0 Tw (FPGA.) Tj 5.76 -19.92 TD 0.079 Tc -0.415 Tw (The first decision to make was the number of registers really required. Looking at C expressions,) Tj -5.76 -13.92 TD 0.054 Tc 0.6942 Tw (it turns out that in most nodes of the parsing tree generated by the compiler consists of expres-) Tj 0 -14.16 TD 0.0736 Tc 0.2169 Tw (sions with a left and a right argument. Thus I gave the CPU two registers called LL and RR; LL) Tj 0 -13.92 TD 0.0439 Tc -0.4392 Tw (holds the left argument of a binary operator, RR the right argument, and the result would be stored) Tj T* 0.0972 Tc 0.6934 Tw (in back in RR. For function calls and local variables, a stack pointer, SP, would be required as) Tj 0 -14.16 TD 0.0697 Tc -0.224 Tw (well. This leads to only three registers LL, RR, and SP. and that is enough.) Tj 5.76 -19.92 TD 0.053 Tc -0.069 Tw (The next question is that of addressing modes required. Another common wisdom is that a good) Tj -5.76 -13.92 TD 0.0439 Tc 0.4079 Tw (instruction set is orthogonal, and this turns out to be as wrong as the believe that many registers) Tj 0 -14.16 TD 0.0937 Tc 0.2213 Tw (are good. In fact, what the compiler really needs is sufficient addressing modes for the leaves of) Tj 0 -13.92 TD 0.0723 Tc 0.1997 Tw (the parse tree \(which are always constants and variables\). Thus the instruction set should be rich) Tj T* 0.0729 Tc 2.4748 Tw (in immediate addressing \(e.g. for ++, --, and frequently used binary operators\), SP relative) Tj 0 -14.16 TD 0.0819 Tc 0.0927 Tw (addressing including pre-decrement and post increment for local variables, and absolute address-) Tj 0 -13.92 TD 0.0949 Tc 0.2308 Tw (ing for global variables. Orthogonality is not required for these addressing modes, it is sufficient) Tj T* 0.0889 Tc -0.3289 Tw (to have immediate addressing for the RR register only for most binary C operands, while absolute) Tj 0 -14.16 TD 0.0993 Tc -0.1993 Tw (addressing helps also for LL register if a variable is a left operand.) Tj 5.76 -19.92 TD 0.0741 Tc -0.3541 Tw (Another thing to get rid of was a flag register. Considering that in C you can have constructs like) Tj 22.56 -19.92 TD /F0 12 Tf 0.0171 Tc -0.0571 Tw (if \(x > y\)) Tj 113.52 0 TD /F1 12 Tf 0.18 Tc -0.42 Tw (as well as) Tj -113.52 -20.16 TD /F0 12 Tf -0.0343 Tc 0.1543 Tw (z = \(x > y\)) Tj -22.56 -19.92 TD /F1 12 Tf 0.04 Tc 0.5 Tw (it makes more sense to have an opcode for a binary operator ) Tj -2.64 Tc 0 Tw (\221) Tj 0 Tc (>) Tj -2.64 Tc 3.12 Tw (\222 ) Tj -0.01 Tc 0.61 Tw (rather than a compare opcode) Tj -5.76 -13.92 TD 0.0259 Tc 0.4301 Tw (CMP, which sets a flag that needs to be checked later on. The good old 68000 had such a set of) Tj 0 -14.16 TD 0.03 Tc -0.0833 Tw (opcodes \(Scc - set according to condition cc\). Thus the decision was to provide a rich set of com-) Tj 0 -13.92 TD 0.0789 Tc -0.3349 Tw (parison operators and only a limited number of conditional branches \(JMP RRZ and JMP RRNZ -) Tj T* 0.0881 Tc 0.1119 Tw (jump in RR is zero resp. non-zero\) instead of a single compare instruction and a rich set of jump) Tj 0 -14.16 TD 0.0538 Tc -0.1411 Tw (instructions. As a consequence, there is no flag register in our CPU.) Tj 5.76 -19.92 TD 0.0611 Tc -0.4011 Tw (The CPU operates on 16 bit quantities only; conversion to and from ) Tj 325.2 0 TD /F0 12 Tf -0.06 Tc 0 Tw (char) Tj 23.52 0 TD /F1 12 Tf 0.0667 Tc -0.4027 Tw ( is made when the oper-) Tj -354.48 -13.92 TD 0.0411 Tc 0.3723 Tw (ands are moved into or out of the RR and LL registers \(rather than having the same opcodes for) Tj 0 -14.16 TD 0.0873 Tc -0.4301 Tw (different sizes as with the 68000\), and ) Tj 184.08 0 TD /F0 12 Tf 0 Tc 0 Tw (long) Tj 22.08 0 TD /F1 12 Tf -0.006 Tc -0.2873 Tw ( is not supported. The reason for not supporting ) Tj 229.2 0 TD /F0 12 Tf 0 Tc 0 Tw (long) Tj 21.84 0 TD /F1 12 Tf 0.12 Tc -0.36 Tw ( is) Tj -457.2 -13.92 TD 0.0896 Tc 2.1664 Tw (essentially FPGA size. A byte operand move into a register is either zero extended or sign) Tj 0 -13.92 TD 0.0425 Tc 0.0563 Tw (extended, as dictated by the opcode. In the assembler, we use the notation RU \(R unsigned\) for a) Tj 0 -14.16 TD 0.0577 Tc -0.2844 Tw (byte operand that is zero extended, RS \(R signed\) for a byte operand that is sign extended and RR) Tj 0 -13.92 TD 0.0354 Tc -0.1462 Tw (for a word operand. Likewise LU, LS, and LL for the left operand register.) Tj 5.76 -19.92 TD 0.0584 Tc 0.8483 Tw (Most immediate operands and SP offsets can be short \(8 bit wide\) or long \(16 bit wide\) as to) Tj -5.76 -14.16 TD 0.0457 Tc -0.2057 Tw (reduce the program size.) Tj 0 -36 TD /F0 18 Tf 0.12 Tc 0 Tw (2) Tj 56.64 0 TD -0.03 Tc (Installation) Tj -50.88 -23.04 TD /F1 12 Tf 0.1108 Tc -0.3084 Tw (The CPU comes with an assembler, a C compiler, a simulator, and a few simple utilities for gen-) Tj -5.76 -13.92 TD 0.0997 Tc 0.3803 Tw (erating VHDL files for the internal memory of the FPGA, communicating with serial ports on a) Tj 0 -13.92 TD 0.0551 Tc 0.2413 Tw (PC, and so on. Everything has been tested on Windows XP, but should also work on other Win-) Tj ET endstream endobj 14 0 obj 5395 endobj 12 0 obj << /Type /Page /Parent 5 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 13 0 R >> endobj 16 0 obj << /Length 17 0 R >> stream BT 72 712.08 TD 0 0 0 rg /F1 12 Tf 0.093 Tc 0.1188 Tw (dows versions as well as Linux. I personally prefer Linux, but the fact that my Xilinx tools work) Tj 0 -14.16 TD 0.0724 Tc -0.2016 Tw (under Windows has kind of forced me to do the entire development on Windows.) Tj 0 -29.28 TD /F0 13.92 Tf -0.04 Tc 0 Tw (2.1) Tj 56.64 0 TD 0.0513 Tc (Prerequisites) Tj -50.88 -18.72 TD /F1 12 Tf 0.0576 Tc -0.1605 Tw (For Windows XP, you can use the ) Tj 167.04 0 TD /F0 12 Tf 0.03 Tc 0 Tw (.exe) Tj 19.68 0 TD /F1 12 Tf 0.1371 Tc -0.2571 Tw ( files provided.) Tj -186.72 -19.92 TD 0.06 Tc -0.2446 Tw (For other Windows versions, the tools provided may or may not work without recompilation.) Tj 0 -19.92 TD 0.0655 Tc -0.2026 Tw (For Linux you need to compile the tools.) Tj 0 -20.16 TD 0.1108 Tc -0.3165 Tw (When compilation is required, you should have ) Tj 229.68 0 TD /F0 12 Tf 0.048 Tc 0 Tw (gmake) Tj 33.84 0 TD /F1 12 Tf -0.24 Tc 0.24 Tw (, ) Tj 6 0 TD /F0 12 Tf 0.08 Tc 0 Tw (gcc) Tj 16.56 0 TD /F1 12 Tf -0.24 Tc 0.24 Tw (, ) Tj 5.76 0 TD /F0 12 Tf -0.024 Tc 0 Tw (bison) Tj 27.36 0 TD /F1 12 Tf 0.06 Tc -0.18 Tw (, and ) Tj 26.16 0 TD /F0 12 Tf -0.12 Tc 0 Tw (flex) Tj 18.72 0 TD /F1 12 Tf 0.1067 Tc -0.3467 Tw (. The following sites) Tj -369.84 -13.92 TD 0.042 Tc -0.1106 Tw (are useful for getting these tools for Windows:) Tj 56.64 -40.08 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD 0.0554 Tc (www.mingw.org) Tj 113.52 0 TD 0 Tc (\(gcc\)) Tj -170.16 -13.92 TD -2.64 Tc (\225) Tj 56.64 0 TD -0.0218 Tc (www.gnu.org) Tj 113.52 0 TD 0.1067 Tc -0.1067 Tw (\(gmake, bison, flex\)) Tj -221.04 -34.08 TD 0.12 Tc -0.2 Tw (Even if you don) Tj -2.64 Tc 0 Tw (\222) Tj 0.09 Tc -0.234 Tw (t compile, I would recommend ) Tj 231.36 0 TD /F0 12 Tf 0 Tc 0 Tw (gmake) Tj 34.08 0 TD /F1 12 Tf 0.08 Tc -0.2 Tw ( and ) Tj 23.28 0 TD /F0 12 Tf 0 Tc 0 Tw (gcc) Tj 16.56 0 TD /F1 12 Tf 0.0662 Tc -0.1862 Tw ( at least. Our compiler does little) Tj -311.04 -13.92 TD 0.1003 Tc 0.3797 Tw (type checking, so you should syntax-check your own files with gcc before running the compiler) Tj 0 -13.92 TD 0.0267 Tc 0 Tw (provided.) Tj 0 -29.52 TD /F0 13.92 Tf -0.04 Tc (2.2) Tj 56.64 0 TD 0.0664 Tc -0.1864 Tw (Directory Structure) Tj -50.88 -18.48 TD /F1 12 Tf 0.065 Tc -0.145 Tw (The entire package contains the following directories:) Tj 50.88 -40.08 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf 0.04 Tc (asm) Tj 113.52 0 TD /F1 12 Tf 0.048 Tc -0.168 Tw (source code for the assembler) Tj -170.16 -13.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf 0 Tc (compiler) Tj 113.52 0 TD /F1 12 Tf 0.0384 Tc -0.1344 Tw (source code for the C compiler) Tj -170.16 -14.16 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf 0 Tc (doc) Tj 113.52 0 TD /F1 12 Tf 0.084 Tc -0.204 Tw (contains this document) Tj -170.16 -13.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf 0.08 Tc (memory) Tj 113.52 0 TD /F1 12 Tf 0.016 Tc -0.176 Tw (utility to create ) Tj 74.88 0 TD /F0 12 Tf 0.018 Tc 0 Tw (vhdl/mem_content.vhd) Tj 117.6 0 TD /F1 12 Tf 0.08 Tc -0.56 Tw ( and) Tj 19.92 0 TD /F0 12 Tf 0 Tc -0.36 Tw ( vhdl/) Tj -212.4 -13.92 TD -0.0277 Tc 0 Tw (board_cpu.ucf) Tj 74.16 0 TD /F1 12 Tf 0.1407 Tc -0.2367 Tw ( \(Xilinx and Avnet board specific\)) Tj -244.32 -14.16 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf 0.04 Tc (sim) Tj 113.52 0 TD /F1 12 Tf 0.0288 Tc -0.1488 Tw (source code for the simulator) Tj -170.16 -13.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf -0.06 Tc (vhdl) Tj 113.52 0 TD /F1 12 Tf 0.0424 Tc -0.1624 Tw (vhdl code for the CPU) Tj -226.8 -29.28 TD /F0 13.92 Tf -0.04 Tc 0 Tw (2.3) Tj 56.64 0 TD 0.0196 Tc 0.0524 Tw (Makefiles and Building the Base System) Tj -50.88 -18.72 TD /F1 12 Tf 0.075 Tc -0.235 Tw (There are 3 different targets for the top level Makefile.) Tj 50.88 -40.08 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf -0.04 Tc (loader) Tj 113.52 0 TD /F1 12 Tf 0.0923 Tc -0.2423 Tw (a small program that loads a subsequent memory ) Tj 0 -13.92 TD 0.0758 Tc -0.2198 Tw (image from the serial port of the FPGA into the ) Tj T* 0 Tc 0 Tw (CPU) Tj -2.64 Tc (\222) Tj 0.15 Tc -0.39 Tw (s memory.) Tj -170.16 -14.16 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf 0.03 Tc (test) Tj 113.52 0 TD /F1 12 Tf 0.066 Tc -0.186 Tw (a small monitor program for testing various I/O ) Tj 0 -13.92 TD 0.08 Tc -0.24 Tw (functions of the FPGA) Tj -170.16 -13.92 TD /F0 12 Tf -2.76 Tc 0 Tw (\225) Tj 56.64 0 TD 0 Tc (rtos) Tj 113.52 0 TD /F1 12 Tf 0.0884 Tc -0.2804 Tw (the same monitor as for ) Tj 116.16 0 TD /F0 12 Tf 0.03 Tc 0 Tw (test) Tj 18 0 TD /F1 12 Tf 0.0706 Tc -0.1906 Tw (, but using a preemp-) Tj -134.16 -14.16 TD 0.0852 Tc -0.1652 Tw (tive multitasking operating system) Tj ET endstream endobj 17 0 obj 4935 endobj 15 0 obj << /Type /Page /Parent 5 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 16 0 R >> endobj 19 0 obj << /Length 20 0 R >> stream BT 77.76 712.08 TD 0 0 0 rg /F1 12 Tf 0.0927 Tc -0.2927 Tw (The anticipated development process is as follows.) Tj 50.88 -20.16 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD 0.08 Tc -0.24 Tw (Copy the CPU package on your machine) Tj -56.64 -13.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD 0.1292 Tc -0.3692 Tw (Either install ) Tj 63.84 0 TD /F0 12 Tf 0 Tc 0 Tw (gmake) Tj 34.08 0 TD /F1 12 Tf 0.0545 Tc -0.5825 Tw ( \(recommended\) or else perform the actions in the top ) Tj -97.92 -13.92 TD 0.24 Tc -0.24 Tw (level ) Tj 26.4 0 TD /F0 12 Tf -0.03 Tc 0 Tw (Makefile) Tj 45.36 0 TD /F1 12 Tf 0.135 Tc -0.215 Tw ( manually later on.) Tj -128.4 -14.16 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD 0.1084 Tc -0.1484 Tw (Build the utilities if required \(see ) Tj 162 0 TD 0.072 Tc -0.168 Tw (2.1 regarding when this is needed\).) Tj -218.64 -13.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD 0.102 Tc -0.27 Tw (If you have a Virtex E evaluation kit from Avnet \() Tj 241.2 0 TD /F0 12 Tf -0.0086 Tc 0 Tw (ADS-XLX-VE-EVL) Tj 102.72 0 TD /F1 12 Tf -0.24 Tc 0.24 Tw (, ) Tj -343.92 -13.92 TD 0.0185 Tc -0.3385 Tw ($150\), then the ) Tj 74.4 0 TD /F0 12 Tf -0.12 Tc 0 Tw (vhdl) Tj 22.56 0 TD /F1 12 Tf 0.0587 Tc -0.495 Tw ( files are ok already. Otherwise, you need to adapt the ) Tj -96.96 -14.16 TD 0.18 Tc -0.24 Tw (top level vhdl file ) Tj 88.08 0 TD /F0 12 Tf -0.02 Tc 0 Tw (vhdl/board_cpu.vhd) Tj 103.68 0 TD /F1 12 Tf 0.1477 Tc -0.2437 Tw ( and the UCF file ) Tj 86.16 0 TD /F0 12 Tf 0 Tc 0 Tw (vhdl/) Tj -277.92 -13.92 TD -0.0277 Tc (board_cpu.ucf) Tj 74.4 0 TD /F1 12 Tf 0.0588 Tc -0.517 Tw ( \(for the Xilinx design flow\) to your actual hardware. Note ) Tj -74.4 -13.92 TD 0.0857 Tc -0.1657 Tw (that the utility ) Tj 70.32 0 TD /F0 12 Tf 0.0514 Tc 0 Tw (memory/makemem) Tj 99.36 0 TD /F1 12 Tf 0.128 Tc -0.308 Tw ( will overwrite the UCF file, so when ) Tj -169.68 -14.16 TD 0.112 Tc -0.24 Tw (you use a different UCF file, then you should use a different name for it, ) Tj 0 -13.92 TD 0.0579 Tc -0.2179 Tw (so that it will not be overwritten,) Tj -56.64 -13.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD -0.12 Tc 0.12 Tw (Do ) Tj 17.52 0 TD /F0 12 Tf -0.024 Tc -0.096 Tw (make loader) Tj 63.36 0 TD /F1 12 Tf 0.1029 Tc -0.4329 Tw ( in the top level directory. This compiles ) Tj 195.6 0 TD /F0 12 Tf 0.015 Tc 0 Tw (loader.c) Tj 40.8 0 TD /F1 12 Tf 0 Tc -0.24 Tw ( \(gener-) Tj -317.28 -14.16 TD 0.096 Tc -0.096 Tw (ating ) Tj 27.12 0 TD /F0 12 Tf 0 Tc 0 Tw (loader.asm) Tj 56.16 0 TD /F1 12 Tf 0.1309 Tc -0.1309 Tw (\), assembles ) Tj 61.68 0 TD /F0 12 Tf 0 Tc 0 Tw (loader.asm) Tj 56.4 0 TD /F1 12 Tf 0.1636 Tc -0.3076 Tw ( \(generating a binary file ) Tj -201.36 -13.92 TD /F0 12 Tf -0.012 Tc 0 Tw (loader.bin) Tj 52.32 0 TD /F1 12 Tf 0.192 Tc -0.288 Tw (, an intel hex file ) Tj 84 0 TD /F0 12 Tf -0.036 Tc 0 Tw (loader.ihx) Tj 51.6 0 TD /F1 12 Tf 0.2 Tc -0.296 Tw ( and a list file ) Tj 68.4 0 TD /F0 12 Tf 0.012 Tc 0 Tw (loader.lst) Tj 47.52 0 TD /F1 12 Tf 0 Tc (\), and cre-) Tj -303.84 -13.92 TD (ates ) Tj 21.84 0 TD /F0 12 Tf 0.018 Tc (vhdl/mem_content.vhd) Tj 117.6 0 TD /F1 12 Tf 0.144 Tc -0.204 Tw ( using the utility ) Tj 81.12 0 TD /F0 12 Tf 0.0686 Tc 0 Tw (makemem) Tj 53.28 0 TD /F1 12 Tf 0 Tc (\).) Tj -330.48 -14.16 TD -2.64 Tc (\225) Tj 56.64 0 TD 0.0369 Tc -0.1269 Tw (Compile the VHDL code and download to the FPGA.) Tj -107.52 -33.84 TD 0.0726 Tc 0.1274 Tw (At this point, you should have a working system on a chip. When you connect to the serial port) Tj -5.76 -14.16 TD 0.0273 Tc -0.2407 Tw (of the FPGA \(115,200 kBaud, 8 data bits, no parity, no flow control\) and reset the FPGA, the sys-) Tj 0 -13.92 TD 0.0709 Tc -0.2209 Tw (tem should print the following on the serial output:) Tj 28.32 -19.92 TD /F0 12 Tf -0.048 Tc 0.168 Tw (LOAD >) Tj -22.56 -20.16 TD /F1 12 Tf 0.0911 Tc 0.6571 Tw (This means the system is ready to load the desired application as a series of intel hex records.) Tj -5.76 -13.92 TD 0.0527 Tc -0.4577 Tw (Every intel hex record loaded will be acknowledge by a dot printed on the serial output. Corrupted) Tj 0 -13.92 TD 0.0447 Tc 0.0153 Tw (characters or records are indicated by the message ) Tj 245.28 0 TD /F0 12 Tf -0.03 Tc 0.27 Tw (ERROR: not hex) Tj 88.32 0 TD /F1 12 Tf 0.0923 Tc -0.0123 Tw ( \(invalid character received,) Tj -333.6 -14.16 TD -0.036 Tc -0.012 Tw (check baud rate etc.\) or ) Tj 115.2 0 TD /F0 12 Tf -0.0092 Tc 0.1292 Tw (CHECKSUM ERROR) Tj 116.88 0 TD /F1 12 Tf 0.0672 Tc -0.1272 Tw ( \(rather unlikely to happen\).) Tj -232.08 -29.28 TD /F0 13.92 Tf -0.04 Tc 0 Tw (2.4) Tj 56.64 0 TD 0.0214 Tc -0.1414 Tw (Building Applications) Tj -50.88 -18.72 TD /F1 12 Tf 0.084 Tc 0.0189 Tw (After the base system containing the loader is working, you can develop your own applications.) Tj -5.76 -13.92 TD 0.0454 Tc -0.114 Tw (Two applications are provided with the CPU: ) Tj 220.8 0 TD /F0 12 Tf 0.03 Tc 0 Tw (test) Tj 18 0 TD /F1 12 Tf 0.16 Tc -0.28 Tw ( and ) Tj 23.28 0 TD /F0 12 Tf 0 Tc 0 Tw (rtos) Tj 20.16 0 TD /F1 12 Tf (.) Tj -276.48 -19.92 TD 0.1029 Tc -0.2229 Tw (To build the application ) Tj 117.84 0 TD /F0 12 Tf 0.03 Tc 0 Tw (test) Tj 18 0 TD /F1 12 Tf 0 Tc -0.12 Tw (, just do) Tj -113.28 -20.16 TD /F0 12 Tf 0.015 Tc 0.105 Tw (make test) Tj -22.56 -19.92 TD /F1 12 Tf 0.048 Tc -0.168 Tw (which creates \(among others\) ) Tj 144.48 0 TD /F0 12 Tf -0.03 Tc 0 Tw (test.ihx) Tj 36.96 0 TD /F1 12 Tf 0.0761 Tc -0.1634 Tw (, which can be loaded into the FPGA via the loader. ) Tj 251.76 0 TD /F0 12 Tf 0.03 Tc 0 Tw (test) Tj 18 0 TD /F1 12 Tf 0.12 Tc -0.12 Tw ( is) Tj -456.96 -13.92 TD 0.1184 Tc 0.9958 Tw (a small monitor that has functions for displaying and modifying memory, setting LEDs on the) Tj 0 -14.16 TD 0.0243 Tc -0.1243 Tw (board, reading the DIP switches on the board, and reading the temperature sensor.) Tj 5.76 -19.92 TD 0.1829 Tc -0.3269 Tw (I was initially using the ) Tj 115.2 0 TD /F0 12 Tf -0.0092 Tc 0 Tw (HyperTerminal) Tj 80.64 0 TD /F1 12 Tf 0.0764 Tc -0.2564 Tw ( program shipped with Windows XP, but copying \(intel) Tj -201.6 -13.92 TD 0.0431 Tc -0.269 Tw (hex\) files to the FPGA was very slow \(even though the baud rate was 115,200\). Therefore I wrote) Tj 0 -14.16 TD 0.0904 Tc 0.081 Tw (the tty.exe program supplied in the package which dumps files much faster on COM1. ) Tj 421.44 0 TD /F0 12 Tf 0 Tc 0 Tw (tty) Tj 13.92 0 TD /F1 12 Tf -0.096 Tc 0.336 Tw ( works) Tj -435.36 -13.92 TD 0.091 Tc -0.091 Tw (from the DOS command line \(program ) Tj 190.56 0 TD /F0 12 Tf 0.08 Tc 0 Tw (cmd) Tj 22.08 0 TD /F1 12 Tf 0.1346 Tc -0.1346 Tw ( in Windows XP\) pretty much like HyperTerminal in) Tj -212.64 -13.92 TD 0.0313 Tc -0.1753 Tw (a window. tty is started as:) Tj 28.32 -20.16 TD /F0 12 Tf 0 Tc 0.12 Tw (tty [filename]) Tj ET endstream endobj 20 0 obj 7056 endobj 18 0 obj << /Type /Page /Parent 5 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 19 0 R >> endobj 22 0 obj << /Length 23 0 R >> stream BT 77.76 712.08 TD 0 0 0 rg /F1 12 Tf 0.1333 Tc 0.9707 Tw (If no filename is provided, then) Tj 0 Tc 0 Tw ( ) Tj 161.52 0 TD /F0 12 Tf -0.015 Tc (rtos.ihx) Tj 38.88 0 TD /F1 12 Tf 0.1516 Tc 0.8684 Tw ( is assumed by default.) Tj 0 Tc 0 Tw ( ) Tj 118.56 0 TD /F0 12 Tf 0.08 Tc (tty) Tj 14.16 0 TD /F1 12 Tf 0.06 Tc 0.98 Tw ( prints characters received) Tj -338.88 -14.16 TD 0.12 Tc -0.12 Tw (from ) Tj 26.16 0 TD /F0 12 Tf 0.024 Tc 0 Tw (COM1:) Tj 39.36 0 TD /F1 12 Tf 0 Tc -0.16 Tw ( on the ) Tj 35.04 0 TD /F0 12 Tf 0.08 Tc 0 Tw (cmd) Tj 21.84 0 TD /F1 12 Tf 0.1662 Tc -0.4062 Tw ( window in which ) Tj 88.56 0 TD /F0 12 Tf 0 Tc 0 Tw (tty) Tj 13.92 0 TD /F1 12 Tf 0.0229 Tc -0.2895 Tw ( was started and sends characters typed on the key-) Tj -224.88 -13.92 TD -0.0686 Tc 0.0686 Tw (board to ) Tj 42.96 0 TD /F0 12 Tf 0.024 Tc 0 Tw (COM1:) Tj 39.36 0 TD /F1 12 Tf 0.072 Tc -0.072 Tw (. The special character ) Tj 111.36 0 TD /F0 12 Tf -0.06 Tc 0 Tw (^L) Tj 14.88 0 TD /F1 12 Tf 0.08 Tc -0.08 Tw ( causes ) Tj 37.68 0 TD /F0 12 Tf 0 Tc 0 Tw (tty) Tj 13.92 0 TD /F1 12 Tf 0.0923 Tc -0.0923 Tw ( to copy the file ) Tj 78.96 0 TD /F0 12 Tf 0.0133 Tc 0.1067 Tw (filename \() Tj 51.12 0 TD /F1 12 Tf -0.12 Tc 0.12 Tw (or ) Tj 13.2 0 TD /F0 12 Tf -0.045 Tc 0 Tw (rtos.ihx) Tj 38.88 0 TD /F1 12 Tf 0.3 Tc -0.3 Tw ( if no) Tj -442.32 -13.92 TD 0.24 Tc 0 Tw (filename) Tj 42 0 TD /F0 12 Tf 0 Tc 0.12 Tw ( ) Tj 2.88 0 TD /F1 12 Tf 0.0891 Tc -0.1791 Tw (is provided as a command line argument\) to ) Tj 213.84 0 TD /F0 12 Tf 0.024 Tc 0 Tw (COM1:) Tj 39.36 0 TD /F1 12 Tf 0 Tc (.) Tj -292.32 -20.16 TD 0.0384 Tc -0.1717 Tw (Note that there are two different ways to use applications:) Tj 50.88 -19.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD -0.12 Tc 0.12 Tw (Do ) Tj 17.76 0 TD /F0 12 Tf -0.024 Tc 0.144 Tw (make loader) Tj 63.6 0 TD /F1 12 Tf 0.073 Tc -0.217 Tw ( first, compile the vhdl, and download to the FPGA \(typ-) Tj -81.36 -13.92 TD 0.0826 Tc -0.3411 Tw (ically to a serial configuration PROM\). After that, you leave the FPGA as ) Tj 0 -14.16 TD 0.0576 Tc -0.1667 Tw (it is and load applications over the serial port to the FPGA.) Tj -56.64 -13.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD -0.12 Tc 0.12 Tw (Do ) Tj 17.76 0 TD /F0 12 Tf 0.015 Tc 0.105 Tw (make test) Tj 48.96 0 TD /F1 12 Tf 0.05 Tc -0.218 Tw ( \(or rtos, or another application\), compile the vhdl, and ) Tj -66.72 -13.92 TD 0.0842 Tc -0.1715 Tw (download to the FPGA \(typically to a serial configuration PROM only ) Tj 0 -14.16 TD 0.084 Tc -0.184 Tw (when the application is finalized\). This method does not use the loader ) Tj 0 -13.92 TD 0.1011 Tc -0.2211 Tw (and is somewhat simpler, but it also takes much more time for the vhdl ) Tj T* 0.1239 Tc -0.2439 Tw (compilation after every change of the application. This method is fine if ) Tj 0 -14.16 TD 0.0669 Tc -0.4669 Tw (you just want to play around with the code, without developing new appli-) Tj 0 -13.92 TD 0.06 Tc 0 Tw (cations.) Tj -107.52 -34.08 TD 0.09 Tc 2.518 Tw (The rtos application is a stripped down version of n real-time OS kernel which has been) Tj -5.76 -13.92 TD 0.0286 Tc -0.1314 Tw (described earlier \(for the 68000 processor\). See ) Tj 230.4 0 TD /F0 12 Tf -0.0436 Tc 0 Tw (os_book.pdf) Tj 62.4 0 TD /F1 12 Tf 0.0873 Tc -0.3273 Tw ( for details.) Tj -292.8 -36 TD /F0 18 Tf 0.12 Tc 0 Tw (3) Tj 56.64 0 TD -0.0189 Tc 0.0789 Tw (Software Description) Tj -56.64 -31.44 TD /F0 13.92 Tf -0.04 Tc 0 Tw (3.1) Tj 56.64 0 TD 0.0512 Tc 0.0688 Tw (C Compiler) Tj -50.88 -18.48 TD /F0 12 Tf -0.0133 Tc 0 Tw (Synopsis:) Tj 79.2 0 TD 0.0207 Tc -0.0507 Tw (cc80 [ -l ] memtop infile [ outfile ]) Tj -79.2 -20.16 TD 0.0267 Tc 0.0933 Tw (Example 1:) Tj 79.2 0 TD 0 Tc 0.06 Tw (cc80 -l 0x2000 loader.c loader.asm) Tj -79.2 -19.92 TD 0.0267 Tc 0.0933 Tw (Example 2:) Tj 79.2 0 TD 0.005 Tc 0.035 Tw (cc80 0x2000 rtos.c rtos.asm) Tj -79.2 -19.92 TD 0.0267 Tc 0 Tw (Function:) Tj 79.2 0 TD /F1 12 Tf 0.1143 Tc 1.3857 Tw (Compile the C source file) Tj 0 Tc 0 Tw ( ) Tj 134.16 0 TD /F0 12 Tf -0.04 Tc (infile) Tj 26.16 0 TD /F1 12 Tf 0.1152 Tc 1.3728 Tw ( and create the assembler file) Tj 0 Tc 0 Tw ( ) Tj 151.92 0 TD /F0 12 Tf -0.0171 Tc (outfile) Tj 32.64 0 TD /F1 12 Tf -0.04 Tc 1.6 Tw (. The -l) Tj -344.88 -14.16 TD 0.0514 Tc -0.0514 Tw (option creates a slightly different startup code intended for a loader, which cop-) Tj 0 -13.92 TD 0.0621 Tc 2.0819 Tw (ies itself to the top of the memory. memtop is the top of the memory \(for) Tj T* 0.0662 Tc 0.783 Tw (instance, 0x2000 = 8k for FPGA internal memory, or 0xA000 = 40k when an) Tj 0 -14.16 TD 0.072 Tc -0.072 Tw (external SRAM is used\).) Tj -79.2 -19.92 TD /F0 12 Tf 0.03 Tc 0 Tw (Limitations:) Tj 79.2 0 TD /F1 12 Tf -0.045 Tc -0.035 Tw (Not too well tested) Tj 0 -19.92 TD -0.0096 Tc -0.0864 Tw (No support for compound \(i.e. ) Tj 149.04 0 TD /F0 12 Tf 0.02 Tc 0 Tw (struct) Tj 30 0 TD /F1 12 Tf 0.0632 Tc -0.0632 Tw (\) function arguments.) Tj -179.04 -20.16 TD -0.12 Tc 0.12 Tw (No ) Tj 17.76 0 TD /F0 12 Tf -0.06 Tc 0 Tw (long) Tj 22.08 0 TD /F1 12 Tf -0.03 Tc 0.03 Tw ( data type) Tj -39.84 -19.92 TD 0.0835 Tc -0.2168 Tw (Name should be cc16 \(a left-over from the Z80 compiler\)) Tj -84.96 -29.28 TD /F0 13.92 Tf -0.04 Tc 0 Tw (3.2) Tj 56.64 0 TD 0.0576 Tc (Assembler) Tj -50.88 -18.72 TD /F0 12 Tf -0.0133 Tc (Synopsis:) Tj 79.2 0 TD -0.0115 Tc 0.0515 Tw (assembler infile [ binfile [ listfile[ symfile [ ihxfile ] ] ] ]) Tj -79.2 -19.92 TD 0.03 Tc 0 Tw (Example:) Tj 79.2 0 TD 0.0144 Tc -0.0144 Tw (assembler rtos.asm rtos.bin) Tj ET endstream endobj 23 0 obj 5823 endobj 21 0 obj << /Type /Page /Parent 5 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 22 0 R >> endobj 25 0 obj << /Length 26 0 R >> stream BT 77.76 712.08 TD 0 0 0 rg /F0 12 Tf 0.0267 Tc 0 Tw (Function:) Tj 79.2 0 TD /F1 12 Tf 0.1366 Tc 0.8418 Tw (Assemble and link the input assembler file and create \(1\) a binary output file) Tj 0 -14.16 TD 0.0978 Tc 0.5879 Tw (\(used by the simulator and by the ) Tj 169.44 0 TD /F0 12 Tf 0.0343 Tc 0 Tw (makemem) Tj 53.28 0 TD /F1 12 Tf 0.1239 Tc 0.699 Tw ( utility\), \(2\) a list file \(useful for) Tj -222.72 -13.92 TD 0.1088 Tc 1.6112 Tw (debugging\), \(3\) a symbol file \(used by the simulator to display source level) Tj 0 -13.92 TD 0.1389 Tc -0.2932 Tw (symbols in a nice way\), and \(4\) an intel hex file \(used by the loader\).) Tj -79.2 -20.16 TD /F0 12 Tf 0 Tc 0 Tw (Limitations) Tj 59.28 0 TD /F1 12 Tf (:) Tj 19.92 0 TD 0.1565 Tc -0.2765 Tw (Can not link several files.) Tj -84.96 -29.28 TD /F0 13.92 Tf -0.04 Tc 0 Tw (3.3) Tj 56.64 0 TD 0.0624 Tc (Simulator) Tj -50.88 -18.72 TD /F0 12 Tf -0.0133 Tc (Synopsis:) Tj 79.2 0 TD -0.0055 Tc 0.0055 Tw (simulate binfile symfile) Tj -79.2 -19.92 TD 0.03 Tc 0 Tw (Example:) Tj 79.2 0 TD 0.015 Tc -0.135 Tw (simulate test.bin test.sym) Tj -79.2 -19.92 TD 0.0267 Tc 0 Tw (Function:) Tj 79.2 0 TD /F1 12 Tf 0.15 Tc -0.15 Tw (Simulate ) Tj 45.84 0 TD /F0 12 Tf -0.0343 Tc 0 Tw (binfile) Tj 32.64 0 TD /F1 12 Tf 0.0884 Tc -0.1684 Tw ( at instruction level.) Tj -157.68 -20.16 TD /F0 12 Tf 0 Tc 0 Tw (Limitations) Tj 59.28 0 TD /F1 12 Tf (:) Tj 19.92 0 TD 0.0768 Tc -0.3168 Tw (Can not simulate interrupts.) Tj -79.2 -19.92 TD /F0 12 Tf 0.0857 Tc 0 Tw (Comment) Tj 50.64 0 TD /F1 12 Tf 0 Tc (:) Tj 28.56 0 TD 0.1075 Tc -0.1293 Tw (The simulator is useful for debugging the compiler and assembler. If something) Tj 0 -13.92 TD 0.0517 Tc 0.7323 Tw (does not work, check if it works in the simulator. If it works in the simulator,) Tj 0 -14.16 TD 0.0494 Tc -0.3044 Tw (then the error is in the hardware \(vhdl\). If it does not work in the simulator, then) Tj 0 -13.92 TD 0.1 Tc -0.292 Tw (the error is in the compiler.) Tj -84.96 -29.28 TD /F0 13.92 Tf -0.04 Tc 0 Tw (3.4) Tj 56.64 0 TD 0.0974 Tc (Makemem) Tj -50.88 -18.72 TD /F0 12 Tf -0.0133 Tc (Synopsis:) Tj 79.2 0 TD 0.0171 Tc 0.1029 Tw (makemem binfile) Tj -79.2 -19.92 TD 0.03 Tc 0 Tw (Example:) Tj 79.2 0 TD 0.0212 Tc 0.0988 Tw (makemem loader.bin) Tj -79.2 -20.16 TD 0.0267 Tc 0 Tw (Function:) Tj 79.2 0 TD /F1 12 Tf 0 Tc (Create ) Tj 34.32 0 TD /F0 12 Tf 0.0052 Tc (../vhdl/mem_content.vhd) Tj 126.96 0 TD /F1 12 Tf 0.18 Tc -0.3 Tw ( from ) Tj 29.28 0 TD /F0 12 Tf -0.0343 Tc 0 Tw (binfile) Tj 32.64 0 TD /F1 12 Tf 0 Tc (.) Tj -302.4 -19.92 TD /F0 12 Tf (Limitations) Tj 59.28 0 TD /F1 12 Tf (:) Tj 19.92 0 TD 0.1239 Tc 0.91 Tw (Output file name should be a command line argument rather than a fixed file) Tj 0 -13.92 TD 0.18 Tc 0 Tw (name) Tj -84.96 -29.52 TD /F0 13.92 Tf -0.04 Tc (3.5) Tj 56.64 0 TD 0 Tc (Tty) Tj -50.88 -18.48 TD /F0 12 Tf -0.0133 Tc (Synopsis:) Tj 79.2 0 TD -0.024 Tc 0.144 Tw (tty ihxfile) Tj -79.2 -20.16 TD 0.03 Tc 0 Tw (Example:) Tj 79.2 0 TD -0.0327 Tc 0.1527 Tw (tty rtos.ihx) Tj -79.2 -19.92 TD 0.0267 Tc 0 Tw (Function:) Tj 79.2 0 TD /F1 12 Tf 0.0893 Tc -0.1579 Tw (Terminal program for Windows. Typing ^L downloads ) Tj 268.08 0 TD /F0 12 Tf -0.0343 Tc 0 Tw (ihxfile) Tj 32.16 0 TD /F1 12 Tf 0 Tc (.) Tj -379.44 -19.92 TD /F0 12 Tf (Limitations) Tj 59.28 0 TD /F1 12 Tf (:) Tj 19.92 0 TD 0.0429 Tc -0.2029 Tw (Baudrate is fixed to 115, 200 Baud) Tj 0 -20.16 TD 0.0164 Tc -0.1036 Tw (Data format fixed to 8 data bits, 1 stop bit, no parity) Tj -84.96 -29.28 TD /F0 13.92 Tf -0.04 Tc 0 Tw (3.6) Tj 56.64 0 TD 0.0368 Tc (Bin2array) Tj -50.88 -18.72 TD /F0 12 Tf -0.0133 Tc (Synopsis:) Tj 79.2 0 TD -0.015 Tc -0.105 Tw (bin2array binfile) Tj -79.2 -19.92 TD 0.03 Tc 0 Tw (Example:) Tj 79.2 0 TD 0.0063 Tc -0.1263 Tw (bin2array loader.bin) Tj -79.2 -19.92 TD 0.0267 Tc 0 Tw (Function:) Tj 79.2 0 TD /F1 12 Tf 0.0761 Tc -0.2132 Tw (Writes a C array representing binfile to stdout.) Tj -79.2 -20.16 TD /F0 12 Tf 0.0857 Tc 0 Tw (Comment) Tj 50.64 0 TD /F1 12 Tf 0 Tc (:) Tj 28.56 0 TD 0.0812 Tc 0.2327 Tw (Useful for e.g. providing a loader in an application, so that one application can) Tj 0 -13.92 TD 0.0542 Tc -0.1502 Tw (load another application. See array ) Tj 169.92 0 TD /F0 12 Tf 0.03 Tc 0 Tw (loader[]) Tj 40.56 0 TD /F1 12 Tf 0.08 Tc -0.176 Tw ( in rtos.c for an example.) Tj ET endstream endobj 26 0 obj 4556 endobj 24 0 obj << /Type /Page /Parent 5 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 25 0 R >> endobj 29 0 obj << /Length 30 0 R >> stream BT 72 708 TD 0 0 0 rg /F0 18 Tf 0.12 Tc 0 Tw (4) Tj 56.64 0 TD -0.0095 Tc 0.0695 Tw (Hardware Description) Tj -56.64 -31.44 TD /F0 13.92 Tf -0.04 Tc 0 Tw (4.1) Tj 56.64 0 TD 0.0107 Tc (board_cpu.vhd) Tj -50.88 -18.48 TD /F1 12 Tf 0.1629 Tc -0.3229 Tw (This is the top level design file.) Tj 0 -20.16 TD 0.06 Tc -0.1708 Tw (Adaptations to other boards that the Avnet board should be made in this file.) Tj 0 -19.92 TD 0.1357 Tc -0.2557 Tw (Essentially instantiates ) Tj 112.56 0 TD /F0 12 Tf -0.0133 Tc 0 Tw (cpu16.vhd) Tj 53.04 0 TD /F1 12 Tf 0 Tc (.) Tj -171.36 -29.28 TD /F0 13.92 Tf -0.04 Tc (4.2) Tj 56.64 0 TD 0.0016 Tc (cpu16.vhd) Tj -50.88 -18.72 TD /F1 12 Tf 0.0519 Tc -0.1586 Tw (Breaks down the system on a chip into 3 parts:) Tj 50.88 -19.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf -0.0086 Tc (cpu_engine.vhd) Tj 80.4 0 TD /F1 12 Tf -0.24 Tc 0.24 Tw (. ) Tj 33.12 0 TD 0.1171 Tc -0.5704 Tw (This module is the CPU itself, plus 8kByte onchip ) Tj 0 -14.16 TD 0.12 Tc 0 Tw (RAM.) Tj -170.16 -13.92 TD -2.64 Tc (\225) Tj 56.64 0 TD /F0 12 Tf -0.015 Tc (input_output.vhd) Tj 89.76 0 TD /F1 12 Tf 0 Tc ( ) Tj 23.76 0 TD 0.0821 Tc -0.2021 Tw (This module contains the I/O functions of the ) Tj 0 -13.92 TD 0.0324 Tc -0.1224 Tw (Avnet board. You need to rewrite this module ) Tj 0 -14.16 TD 0.0726 Tc -0.2326 Tw (\(and possibly the applications\) for other boards.) Tj -170.16 -13.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf 0 Tc (bin_to_7segment.vhd) Tj 108.96 0 TD /F1 12 Tf 0.0743 Tc -0.1343 Tw (. This module contains a driver that continuously ) Tj 4.56 -13.92 TD 0.054 Tc -0.114 Tw (displays the program counter of the CPU. Useful ) Tj 0 -14.16 TD 0.091 Tc -0.211 Tw (for debugging the system on a chip.) Tj -226.8 -29.28 TD /F0 13.92 Tf -0.04 Tc 0 Tw (4.3) Tj 56.64 0 TD 0.0298 Tc (bin_to_7segment.vhd) Tj -50.88 -18.72 TD /F1 12 Tf 0.098 Tc 1.2353 Tw (This module samples the PC of the CPU at fixed intervals and shows the value on a pair of) Tj -5.76 -13.92 TD 0.0752 Tc -0.1752 Tw (7segment LEDs. This function is specific to the Avnet board providing the LEDs.) Tj 0 -29.28 TD /F0 13.92 Tf -0.04 Tc 0 Tw (4.4) Tj 56.64 0 TD 0 Tc (input_output.vhd) Tj -50.88 -18.72 TD /F1 12 Tf 0.0714 Tc 0.6486 Tw (This module provides a number of I/O functions that can be accessed by the CPU through the) Tj -5.76 -13.92 TD 0.1029 Tc -0.3429 Tw (assembler instructions) Tj 84.96 -20.16 TD /F0 12 Tf 0.06 Tc 0.06 Tw (IN ) Tj 56.88 0 TD 0.0267 Tc -0.1467 Tw (\(port\), RU) Tj 113.28 0 TD /F1 12 Tf 0.08 Tc 0 Tw (and) Tj -170.16 -19.92 TD /F0 12 Tf -0.04 Tc (OUT) Tj 56.88 0 TD 0.06 Tc -0.18 Tw (R, \(port\)) Tj -136.08 -19.92 TD /F1 12 Tf 0.0835 Tc -0.2435 Tw (The ports implemented are:) Tj 152.16 -52.08 TD -0.04 Tc 0.04 Tw (Port Function) Tj 238.56 0 TD -0.12 Tc 0 Tw (IN) Tj 36 0 TD 0 Tc (OUT) Tj -426.48 -24 TD /F0 12 Tf (IN_RX_DATA) Tj 76.56 0 TD /F1 12 Tf 0.0226 Tc -0.219 Tw (: Data to be transmitted on serial output. In polled operation, ) Tj -76.56 -13.92 TD 0.0514 Tc -0.5314 Tw (you need to check ) Tj 88.08 0 TD /F0 12 Tf -0.0133 Tc 0 Tw (IN_STATUS) Tj 66 0 TD /F1 12 Tf 0.0431 Tc -0.4931 Tw ( before sending data. Reading this port resets ) Tj -154.08 -14.16 TD 0.1309 Tc -0.2269 Tw (bits 4 and 0 in ) Tj 71.04 0 TD /F0 12 Tf 0.0133 Tc 0 Tw (IN_STATUS) Tj 66 0 TD /F1 12 Tf 0 Tc (.) Tj 244.56 28.08 TD (0) Tj ET 71.76 156.24 0.48 75.6 re f 453.36 155.76 0.48 76.56 re f 495.84 155.76 0.48 76.56 re f 537.12 156.24 0.48 75.6 re f 71.76 232.32 m 71.76 231.84 l 537.6 231.84 l 537.6 232.32 l h f 72.24 207.6 m 72.24 207.12 l 537.12 207.12 l 537.12 207.6 l h f 72.24 204.96 m 72.24 204.48 l 537.12 204.48 l 537.12 204.96 l h f 71.76 156.24 m 71.76 155.76 l 537.6 155.76 l 537.6 156.24 l h f endstream endobj 30 0 obj 3908 endobj 27 0 obj << /Type /Page /Parent 28 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 29 0 R >> endobj 32 0 obj << /Length 33 0 R >> stream BT 77.76 157.92 TD 0 0 0 rg /F1 12 Tf 0.0554 Tc 0.0779 Tw (The I/O ports are not in the focus of this document, so please refer to the VHDL files regarding) Tj -5.76 -13.92 TD 0.08 Tc 0.1415 Tw (their implementation. You may find the baudrate generator interesting due to its unlimited preci-) Tj 0 -13.92 TD 0.064 Tc -0.204 Tw (sion, and the Rx and Tx parts due to their very low size.) Tj 0 -29.52 TD /F0 13.92 Tf -0.04 Tc 0 Tw (4.5) Tj 56.64 0 TD 0.0141 Tc (cpu_engine.vhd) Tj -50.88 -18.48 TD /F1 12 Tf 0.06 Tc -0.14 Tw (This is the CPU itself. The structure of the ) Tj 206.4 0 TD /F0 12 Tf -0.024 Tc 0 Tw (cpu_engine) Tj 58.08 0 TD /F1 12 Tf 0.14 Tc -0.3 Tw ( is as follows:) Tj -264.24 597.84 TD /F0 12 Tf -0.0133 Tc 0 Tw (IN_STATUS) Tj 66 0 TD /F1 12 Tf 0.0462 Tc -0.1262 Tw (: Status of serial I/O and timer) Tj -66 -13.92 TD 0.016 Tc -0.196 Tw (Bit 7: not used \(0\)) Tj 0 -13.92 TD 0.0758 Tc -0.2067 Tw (Bit 6: 1 iff timer interrupt enabled and timer interrupt has occured) Tj 0 -14.16 TD 0.0876 Tc -0.2248 Tw (Bit 5:1 iff serial Tx interrupt enabled and serial Tx is ready to accept data) Tj 0 -13.92 TD 0.1163 Tc -0.227 Tw (Bit 4:1 iff serial Rx interrupt enabled and serial Rx has received valid data) Tj T* 0.015 Tc -0.195 Tw (Bit 3: :not used \(0\)) Tj 0 -14.16 TD 0.08 Tc -0.28 Tw (Bit 2:1 iff timer interrupt has occured) Tj 0 -13.92 TD 0.0754 Tc -0.1654 Tw (Bit 1:iff serial Tx is ready to accept data) Tj T* 0.1362 Tc -0.2862 Tw (Bit 0:1 iff serial Rx has received valid data) Tj 381.6 111.84 TD 0 Tc 0 Tw (1) Tj -381.6 -133.92 TD /F0 12 Tf -0.0109 Tc (IN_TEMPERAT) Tj 87.36 0 TD /F1 12 Tf 0.036 Tc -0.126 Tw (: current value from temperature sensor \(8 bit 2) Tj -2.64 Tc 0 Tw (\222) Tj 0.09 Tc -0.09 Tw (s comple-) Tj -87.36 -13.92 TD 0.1054 Tc -0.2254 Tw (ment in degrees Celsius\) \(Avnet board specific\)) Tj 381.6 13.92 TD 0 Tc 0 Tw (2) Tj -381.6 -36 TD /F0 12 Tf (IN_DIP_SWITCH) Tj 95.28 0 TD /F1 12 Tf 0.0528 Tc -0.4261 Tw (: current setting of the DIP switch. \(Avnet board specific\)) Tj 286.32 0 TD 0 Tc 0 Tw (3) Tj -381.6 -22.08 TD /F0 12 Tf -0.0086 Tc (IN_CLK_CTR_LOW) Tj 111.84 0 TD /F1 12 Tf 0.0457 Tc -0.1657 Tw (: current value of a 16 bit clock counter \(low byte\)) Tj 269.76 0 TD 0 Tc 0 Tw (4) Tj -381.6 -21.84 TD /F0 12 Tf (IN_CLK_CTR_HIGH) Tj 115.2 0 TD /F1 12 Tf 0.067 Tc -0.2197 Tw (: current value of a 16 bit clock counter \(high byte\)) Tj 266.4 0 TD 0 Tc 0 Tw (5) Tj -381.6 -22.08 TD /F0 12 Tf -0.0109 Tc (OUT_TX_DATA) Tj 88.56 0 TD /F1 12 Tf 0.07 Tc -0.238 Tw (: Data received on serial input. In polled operation, you ) Tj -88.56 -13.92 TD 0 Tc 0 Tw (need to check ) Tj 68.88 0 TD /F0 12 Tf -0.0133 Tc (IN_STATUS) Tj 66 0 TD /F1 12 Tf 0.054 Tc -0.1607 Tw ( before readiing data. Writing this port resets ) Tj -134.88 -14.16 TD 0.1309 Tc -0.2269 Tw (bits 5 and 1 in ) Tj 71.04 0 TD /F0 12 Tf 0.0133 Tc 0 Tw (IN_STATUS) Tj 66 0 TD /F1 12 Tf 0 Tc (.) Tj 287.04 28.08 TD (0) Tj -424.08 -49.92 TD /F0 12 Tf -0.0343 Tc 0.1543 Tw (not used) Tj 424.08 0 TD /F1 12 Tf 0 Tc 0 Tw (1) Tj -424.08 -22.08 TD /F0 12 Tf -0.015 Tc (OUT_LEDS) Tj 63.36 0 TD /F1 12 Tf 0.0261 Tc -0.1461 Tw (: Turns each of the 8 LEDs on or off. 1 turns LED on.\(Avnet ) Tj -63.36 -13.92 TD 0.1029 Tc -0.3429 Tw (board specific\)) Tj 424.08 13.92 TD 0 Tc 0 Tw (2) Tj -424.08 -36 TD /F0 12 Tf 0.02 Tc (OUT_INT_MASK) Tj 95.28 0 TD /F1 12 Tf 0.0587 Tc -0.2114 Tw (: The interrupt maks for Rx, Tx and Timer interrupts. 1 ) Tj -95.28 -13.92 TD 0.1 Tc -0.18 Tw (means interrupt is enabled.) Tj 0 -14.16 TD 0 Tc -0.16 Tw (Bit 7..3: not used) Tj 0 -13.92 TD 0.0821 Tc -0.1621 Tw (Bit 2:Enable Timer interrupt \(1 ms interval\)) Tj T* 0.0785 Tc -0.2385 Tw (Bit 1: Enable Rx Interrupt \(receiver has received valid data\)) Tj 0 -14.16 TD 0.0185 Tc -0.1785 Tw (Bit 0: Enable Tx Interrupt \(transmitter ready to accept data\)) Tj 424.08 70.08 TD 0 Tc 0 Tw (3) Tj -424.08 -91.92 TD /F0 12 Tf -0.024 Tc (OUT_RESET_TIMER) Tj 117.84 0 TD /F1 12 Tf 0.0857 Tc -0.1457 Tw (: Writing clears Timer interrupt) Tj 306.24 0 TD 0 Tc 0 Tw (4) Tj -424.08 -22.08 TD /F0 12 Tf -0.0141 Tc (OUT_START_CLK_CTR) Tj 135.36 0 TD /F1 12 Tf -0.0065 Tc -0.1135 Tw (: Start a 16 bit counter clocked at a rate of 20 ) Tj -135.36 -13.92 TD 0.1111 Tc -0.2611 Tw (MHz. Useful for measuring short intervals with high precision.) Tj 424.08 13.92 TD 0 Tc 0 Tw (5) Tj -424.08 -36 TD /F0 12 Tf -0.0075 Tc (OUT_STOP_CLK_CTR) Tj 126.72 0 TD /F1 12 Tf -0.024 Tc -0.072 Tw (: Stop the 16 bit counter) Tj 25.2 517.92 TD -0.04 Tc 0.04 Tw (Port Function) Tj 238.56 0 TD -0.12 Tc 0 Tw (IN) Tj 36 0 TD 0 Tc (OUT) Tj ET 71.76 178.32 0.48 541.44 re f 453.36 177.84 0.48 542.4 re f 495.84 177.84 0.48 542.4 re f 537.12 178.32 0.48 541.44 re f 71.76 720.24 m 71.76 719.76 l 537.6 719.76 l 537.6 720.24 l h f 72.24 695.52 m 72.24 695.04 l 537.12 695.04 l 537.12 695.52 l h f 72.24 693.12 m 72.24 692.64 l 537.12 692.64 l 537.12 693.12 l h f 71.76 560.16 m 71.76 559.68 l 537.6 559.68 l 537.6 560.16 l h f 71.76 524.16 m 71.76 523.68 l 537.6 523.68 l 537.6 524.16 l h f 71.76 502.32 m 71.76 501.84 l 537.6 501.84 l 537.6 502.32 l h f 71.76 480.24 m 71.76 479.76 l 537.6 479.76 l 537.6 480.24 l h f 71.76 458.16 m 71.76 457.68 l 537.6 457.68 l 537.6 458.16 l h f 71.76 408.24 m 71.76 407.76 l 537.6 407.76 l 537.6 408.24 l h f 71.76 386.16 m 71.76 385.68 l 537.6 385.68 l 537.6 386.16 l h f 71.76 350.16 m 71.76 349.68 l 537.6 349.68 l 537.6 350.16 l h f 71.76 258.24 m 71.76 257.76 l 537.6 257.76 l 537.6 258.24 l h f 71.76 236.16 m 71.76 235.68 l 537.6 235.68 l 537.6 236.16 l h f 71.76 200.16 m 71.76 199.68 l 537.6 199.68 l 537.6 200.16 l h f 71.76 178.32 m 71.76 177.84 l 537.6 177.84 l 537.6 178.32 l h f endstream endobj 33 0 obj 5955 endobj 31 0 obj << /Type /Page /Parent 28 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 32 0 R >> endobj 35 0 obj << /Length 36 0 R >> stream BT 77.76 487.92 TD 0 0 0 rg /F1 12 Tf 0.0512 Tc 0.9088 Tw (The memory signals are also extended to the outside of this module in order to connect to an) Tj -5.76 -13.92 TD 0.0429 Tc -0.1229 Tw (optional external SRAM and to the ) Tj 171.12 0 TD /F0 12 Tf -0.015 Tc 0 Tw (input_output.vhd) Tj 89.76 0 TD /F1 12 Tf 0.1029 Tc -0.3429 Tw ( module.) Tj -255.12 -19.92 TD 0.3105 Tw (The timing is as follows. All signals are clocked on the rising edge of the 40 MHz input clock.) Tj -5.76 -14.16 TD 0.0759 Tc 0.2241 Tw (However, most signals are clocked on every second clock only. This is controlled by the T2 sig-) Tj 0 -13.92 TD 0.0896 Tc -0.0736 Tw (nal. The internal memory is dual-ported, but only to save address and data multiplexers. The first) Tj T* 0.0429 Tc -0.2429 Tw (clock interval \(say T1, or better ) Tj -2.64 Tc 0 Tw (\221) Tj -0.096 Tc -0.144 Tw (not T2) Tj -2.64 Tc 0 Tw (\222) Tj 0.0511 Tc -0.2474 Tw (\) is used for opcode reads, while the second phase \(T2\) is) Tj 0 -14.16 TD 0.041 Tc -0.1953 Tw (used for all other \(that is, operand transfers; immediate operands are counted as opcode reads\).) Tj 5.76 -231.12 TD 0.1103 Tc -0.1103 Tw (We call a full T2 cycle an M cycle; most opcodes use only a single M cycle \(M1\), opcodes with) Tj -5.76 -13.92 TD 0.0448 Tc 0.1387 Tw (a short immediate operand require two M cycles \(M1 and M2\), and so on. The longest opcode is) Tj 0 -13.92 TD 0.0649 Tc 0.1246 Tw (RET, reading the return address in M2 and M3, plus 2 M cycles delay from the PC to the execu-) Tj 0 -14.16 TD 0.063 Tc 0.5541 Tw (tion unit. Opcodes without immediate operands \(addresses or data\) execute in a single M cycle.) Tj 0 -13.92 TD 0.08 Tc 1.008 Tw (Some frequently used operations have a quick mode, where a 4 bit immediate operand is con-) Tj T* 0.0831 Tc 0.7119 Tw (tained in the opcode; these opcodes have an immediate operand, but still execute in a single M) Tj 0 -14.16 TD 0.16 Tc 0 Tw (cycle.) Tj ET 1 1 1 rg 72 523.92 468 184.08 re f 444.72 545.04 84.96 42.48 re f 0 0 0 rg 444.72 585.84 86.64 3.12 re f 528.24 543.36 3.12 44.16 re f 443.28 543.36 86.4 3.12 re f 443.28 545.04 3.12 43.92 re f BT 462 560.88 TD /F0 12 Tf 0.0133 Tc (data_core) Tj ET 1 1 1 rg 260.4 545.04 85.2 42.48 re f 0 0 0 rg 260.4 585.84 86.88 3.12 re f 344.16 543.36 3.12 44.16 re f 258.96 543.36 86.64 3.12 re f 258.96 545.04 3.12 43.92 re f BT 281.76 560.88 TD 0.08 Tc (memory) Tj ET 1 1 1 rg 76.32 545.04 84.96 42.48 re f 0 0 0 rg 76.32 585.84 86.64 3.12 re f 159.84 543.36 3.12 44.16 re f 74.88 543.36 86.4 3.12 re f 74.88 545.04 3.12 43.92 re f BT 85.2 560.88 TD 0.01 Tc (opcode_fetch) Tj ET 1 1 1 rg 253.44 644.16 99.12 42.48 re f 0 0 0 rg 253.44 684.96 100.8 3.12 re f 351.12 642.48 3.12 44.16 re f 252 642.48 100.56 3.12 re f 252 644.16 3.12 43.92 re f BT 261.6 660.24 TD -0.0171 Tc (opcode_decoder) Tj ET 248.88 566.16 m 248.88 569.52 l 249.6 569.28 l 258.96 566.64 l 260.64 566.16 l 258.96 565.68 l 249.6 563.04 l 248.88 562.8 l 248.88 563.52 l 249.36 564 l 258.72 566.64 l 258.96 565.68 l 258.72 565.68 l 249.36 568.32 l 249.6 569.28 l 249.84 568.8 l 249.84 566.16 l h f 248.88 563.52 m 248.88 566.16 l 249.84 566.16 l 249.84 563.52 l h f 249.36 566.16 m 249.36 568.8 l 258.72 566.16 l 249.36 563.52 l h f* 161.04 565.92 0.24 0.48 re f 248.88 565.92 0.24 0.48 re f 161.28 566.4 m 161.28 565.92 l 248.88 565.92 l 248.88 566.4 l h f 357.12 580.56 m 357.12 577.2 l 356.4 577.44 l 347.04 580.08 l 345.36 580.56 l 347.04 581.04 l 356.4 583.68 l 357.12 583.92 l 357.12 583.2 l 356.64 582.72 l 347.28 580.08 l 347.04 581.04 l 347.28 581.04 l 356.64 578.4 l 356.4 577.44 l 356.16 577.92 l 356.16 580.56 l h f 357.12 583.2 m 357.12 580.56 l 356.16 580.56 l 356.16 583.2 l h f 356.64 580.56 m 356.64 577.92 l 347.28 580.56 l 356.64 583.2 l h f* 356.88 580.32 0.24 0.48 re f 444.72 580.32 0.24 0.48 re f 357.12 580.8 m 357.12 580.32 l 444.72 580.32 l 444.72 580.8 l h f 274.56 632.64 m 271.2 632.64 l 271.44 633.36 l 274.08 642.72 l 274.56 644.4 l 275.04 642.72 l 277.68 633.36 l 277.92 632.64 l 277.2 632.64 l 276.72 633.12 l 274.08 642.48 l 275.04 642.72 l 275.04 642.48 l 272.4 633.12 l 271.44 633.36 l 271.92 633.6 l 274.56 633.6 l h f 277.2 632.64 m 274.56 632.64 l 274.56 633.6 l 277.2 633.6 l h f 274.56 633.12 m 271.92 633.12 l 274.56 642.48 l 277.2 633.12 l h f* 274.32 587.52 m 274.32 587.28 l 274.8 587.28 l 274.8 587.52 l h f 274.32 632.64 m 274.32 632.88 l 274.8 632.88 l 274.8 632.64 l h f 274.32 587.52 0.48 45.12 re f 357.12 566.16 m 357.12 562.8 l 356.4 563.04 l 347.04 565.68 l 345.36 566.16 l 347.04 566.64 l 356.4 569.28 l 357.12 569.52 l 357.12 568.8 l 356.64 568.32 l 347.28 565.68 l 347.04 566.64 l 347.28 566.64 l 356.64 564 l 356.4 563.04 l 356.16 563.52 l 356.16 566.16 l h f 357.12 568.8 m 357.12 566.16 l 356.16 566.16 l 356.16 568.8 l h f 356.64 566.16 m 356.64 563.52 l 347.28 566.16 l 356.64 568.8 l h f* 356.88 565.92 0.24 0.48 re f 444.72 565.92 0.24 0.48 re f 357.12 566.4 m 357.12 565.92 l 444.72 565.92 l 444.72 566.4 l h f BT 175.44 568.32 TD /F0 9.84 Tf 0.1056 Tc (PC) Tj 106.56 45.84 TD 0.152 Tc (OPC) Tj ET 487.2 599.04 m 490.56 599.04 l 490.32 598.32 l 487.68 589.2 l 487.2 587.52 l 486.72 589.2 l 484.08 598.32 l 483.84 599.04 l 484.56 599.04 l 485.04 598.56 l 487.68 589.44 l 486.72 589.2 l 486.72 589.44 l 489.36 598.56 l 490.32 598.32 l 489.84 598.08 l 487.2 598.08 l h f 484.56 599.04 m 487.2 599.04 l 487.2 598.08 l 484.56 598.08 l h f 487.2 598.56 m 489.84 598.56 l 487.2 589.44 l 484.56 598.56 l h f* 352.32 665.28 0.24 0.48 re f 356.4 665.28 0.24 0.48 re f 352.56 665.76 m 352.56 665.28 l 356.4 665.28 l 356.4 665.76 l h f 362.4 665.28 0.24 0.48 re f* 369.84 665.28 0.24 0.48 re f* 362.64 665.76 m 362.64 665.28 l 369.84 665.28 l 369.84 665.76 l h f* 375.84 665.28 0.24 0.48 re f* 383.28 665.28 0.24 0.48 re f* 376.08 665.76 m 376.08 665.28 l 383.28 665.28 l 383.28 665.76 l h f* 389.28 665.28 0.24 0.48 re f* 396.72 665.28 0.24 0.48 re f* 389.52 665.76 m 389.52 665.28 l 396.72 665.28 l 396.72 665.76 l h f* 402.72 665.28 0.24 0.48 re f* 410.16 665.28 0.24 0.48 re f* 402.96 665.76 m 402.96 665.28 l 410.16 665.28 l 410.16 665.76 l h f* 416.16 665.28 0.24 0.48 re f* 423.6 665.28 0.24 0.48 re f* 416.4 665.76 m 416.4 665.28 l 423.6 665.28 l 423.6 665.76 l h f* 429.6 665.28 0.24 0.48 re f* 437.04 665.28 0.24 0.48 re f* 429.84 665.76 m 429.84 665.28 l 437.04 665.28 l 437.04 665.76 l h f* 443.04 665.28 0.24 0.48 re f* 450.48 665.28 0.24 0.48 re f* 443.28 665.76 m 443.28 665.28 l 450.48 665.28 l 450.48 665.76 l h f* 456.48 665.28 0.24 0.48 re f* 463.92 665.28 0.24 0.48 re f* 456.72 665.76 m 456.72 665.28 l 463.92 665.28 l 463.92 665.76 l h f* 469.92 665.28 0.24 0.48 re f* 477.36 665.28 0.24 0.48 re f* 470.16 665.76 m 470.16 665.28 l 477.36 665.28 l 477.36 665.76 l h f* 483.36 665.28 0.24 0.48 re f 483.6 665.28 3.84 0.48 re f 487.44 661.68 m 487.44 661.44 l 486.96 661.44 l 486.96 661.68 l h f 486.96 661.68 0.48 3.84 re f 487.44 655.68 m 487.44 655.92 l 486.96 655.92 l 486.96 655.68 l h f* 487.44 648.48 m 487.44 648.24 l 486.96 648.24 l 486.96 648.48 l h f* 486.96 648.48 0.48 7.2 re f* 487.44 642.48 m 487.44 642.72 l 486.96 642.72 l 486.96 642.48 l h f* 487.44 635.28 m 487.44 635.04 l 486.96 635.04 l 486.96 635.28 l h f* 486.96 635.28 0.48 7.2 re f* 487.44 629.28 m 487.44 629.52 l 486.96 629.52 l 486.96 629.28 l h f* 487.44 622.08 m 487.44 621.84 l 486.96 621.84 l 486.96 622.08 l h f* 486.96 622.08 0.48 7.2 re f* 487.44 616.08 m 487.44 616.32 l 486.96 616.32 l 486.96 616.08 l h f* 487.44 608.88 m 487.44 608.64 l 486.96 608.64 l 486.96 608.88 l h f* 486.96 608.88 0.48 7.2 re f* 487.44 602.88 m 487.44 603.12 l 486.96 603.12 l 486.96 602.88 l h f 487.44 599.04 m 487.44 598.8 l 486.96 598.8 l 486.96 599.04 l h f 486.96 599.04 0.48 3.84 re f 118.8 599.04 m 122.16 599.04 l 121.92 598.32 l 119.28 589.2 l 118.8 587.52 l 118.32 589.2 l 115.68 598.32 l 115.44 599.04 l 116.16 599.04 l 116.64 598.56 l 119.28 589.44 l 118.32 589.2 l 118.32 589.44 l 120.96 598.56 l 121.92 598.32 l 121.44 598.08 l 118.8 598.08 l h f 116.16 599.04 m 118.8 599.04 l 118.8 598.08 l 116.16 598.08 l h f 118.8 598.56 m 121.44 598.56 l 118.8 589.44 l 116.16 598.56 l h f* 253.44 658.08 0.24 0.48 re f 249.36 658.08 0.24 0.48 re f 253.44 658.08 m 253.44 658.56 l 249.6 658.56 l 249.6 658.08 l h f 243.36 658.08 0.24 0.48 re f* 235.92 658.08 0.24 0.48 re f* 243.36 658.08 m 243.36 658.56 l 236.16 658.56 l 236.16 658.08 l h f* 229.92 658.08 0.24 0.48 re f* 222.48 658.08 0.24 0.48 re f* 229.92 658.08 m 229.92 658.56 l 222.72 658.56 l 222.72 658.08 l h f* 216.48 658.08 0.24 0.48 re f* 209.04 658.08 0.24 0.48 re f* 216.48 658.08 m 216.48 658.56 l 209.28 658.56 l 209.28 658.08 l h f* 203.04 658.08 0.24 0.48 re f* 195.6 658.08 0.24 0.48 re f* 203.04 658.08 m 203.04 658.56 l 195.84 658.56 l 195.84 658.08 l h f* 189.6 658.08 0.24 0.48 re f* 182.16 658.08 0.24 0.48 re f* 189.6 658.08 m 189.6 658.56 l 182.4 658.56 l 182.4 658.08 l h f* 176.16 658.08 0.24 0.48 re f* 168.72 658.08 0.24 0.48 re f* 176.16 658.08 m 176.16 658.56 l 168.96 658.56 l 168.96 658.08 l h f* 162.72 658.08 0.24 0.48 re f* 155.28 658.08 0.24 0.48 re f* 162.72 658.08 m 162.72 658.56 l 155.52 658.56 l 155.52 658.08 l h f* 149.28 658.08 0.24 0.48 re f* 141.84 658.08 0.24 0.48 re f* 149.28 658.08 m 149.28 658.56 l 142.08 658.56 l 142.08 658.08 l h f* 135.84 658.08 0.24 0.48 re f* 128.4 658.08 0.24 0.48 re f* 135.84 658.08 m 135.84 658.56 l 128.64 658.56 l 128.64 658.08 l h f* 122.4 658.08 0.24 0.48 re f 118.56 658.08 3.84 0.48 re f 119.04 654.72 m 119.04 654.48 l 118.56 654.48 l 118.56 654.72 l h f 118.56 654.72 0.48 3.6 re f 119.04 647.76 m 119.04 648 l 118.56 648 l 118.56 647.76 l h f* 119.04 639.6 m 119.04 639.36 l 118.56 639.36 l 118.56 639.6 l h f* 118.56 639.6 0.48 8.16 re f* 119.04 632.64 m 119.04 632.88 l 118.56 632.88 l 118.56 632.64 l h f* 119.04 624.72 m 119.04 624.48 l 118.56 624.48 l 118.56 624.72 l h f* 118.56 624.72 0.48 7.92 re f* 119.04 617.76 m 119.04 618 l 118.56 618 l 118.56 617.76 l h f* 119.04 609.84 m 119.04 609.6 l 118.56 609.6 l 118.56 609.84 l h f* 118.56 609.84 0.48 7.92 re f* 119.04 602.88 m 119.04 603.12 l 118.56 603.12 l 118.56 602.88 l h f 119.04 599.04 m 119.04 598.8 l 118.56 598.8 l 118.56 599.04 l h f 118.56 599.04 0.48 3.84 re f 324.24 599.04 m 327.6 599.04 l 327.36 598.32 l 324.72 589.2 l 324.24 587.52 l 323.76 589.2 l 321.12 598.32 l 320.88 599.04 l 321.6 599.04 l 322.08 598.56 l 324.72 589.44 l 323.76 589.2 l 323.76 589.44 l 326.4 598.56 l 327.36 598.32 l 326.88 598.08 l 324.24 598.08 l h f 321.6 599.04 m 324.24 599.04 l 324.24 598.08 l 321.6 598.08 l h f 324.24 598.56 m 326.88 598.56 l 324.24 589.44 l 321.6 598.56 l h f* 324.48 644.16 m 324.48 644.4 l 324 644.4 l 324 644.16 l h f 324.48 640.56 m 324.48 640.32 l 324 640.32 l 324 640.56 l h f 324 640.56 0.48 3.6 re f 324.48 633.36 m 324.48 633.6 l 324 633.6 l 324 633.36 l h f* 324.48 625.2 m 324.48 624.96 l 324 624.96 l 324 625.2 l h f* 324 625.2 0.48 8.16 re f* 324.48 618 m 324.48 618.24 l 324 618.24 l 324 618 l h f* 324.48 609.84 m 324.48 609.6 l 324 609.6 l 324 609.84 l h f* 324 609.84 0.48 8.16 re f* 324.48 602.88 m 324.48 603.12 l 324 603.12 l 324 602.88 l h f 324.48 599.04 m 324.48 598.8 l 324 598.8 l 324 599.04 l h f 324 599.04 0.48 3.84 re f BT 118.8 660.48 TD 0.0871 Tc (CONTROL) Tj 318 7.2 TD (CONTROL) Tj -105.36 -46.56 TD (CONTROL) Tj 56.64 -38.4 TD 0.1152 Tc (ADR) Tj -14.16 -28.56 TD 0.1182 Tc (RDAT) Tj ET 433.2 552 m 433.2 555.36 l 433.92 555.12 l 443.04 552.48 l 444.72 552 l 443.04 551.52 l 433.92 548.88 l 433.2 548.64 l 433.2 549.36 l 433.68 549.84 l 442.8 552.48 l 443.04 551.52 l 442.8 551.52 l 433.68 554.16 l 433.92 555.12 l 434.16 554.64 l 434.16 552 l h f 433.2 549.36 m 433.2 552 l 434.16 552 l 434.16 549.36 l h f 433.68 552 m 433.68 554.64 l 442.8 552 l 433.68 549.36 l h f* 345.36 551.76 0.24 0.48 re f 433.2 551.76 0.24 0.48 re f 345.6 552.24 m 345.6 551.76 l 433.2 551.76 l 433.2 552.24 l h f BT 388.08 568.32 TD 0.0294 Tc (WDAT) Tj ET 239.04 679.68 m 239.04 683.76 l 239.76 683.52 l 251.76 680.16 l 253.44 679.68 l 251.76 679.2 l 239.76 675.6 l 239.04 675.36 l 239.04 676.08 l 239.52 676.56 l 251.52 680.16 l 251.76 679.2 l 251.52 679.2 l 239.52 682.56 l 239.76 683.52 l 240 683.04 l 240 679.68 l h f 239.04 676.08 m 239.04 679.68 l 240 679.68 l 240 676.08 l h f 239.52 679.68 m 239.52 683.04 l 251.52 679.68 l 239.52 676.08 l h f* 217.44 679.2 0.48 0.96 re f 239.04 679.2 0.48 0.96 re f 217.92 680.16 m 217.92 679.2 l 239.04 679.2 l 239.04 680.16 l h f BT 193.2 675.12 TD 0.0816 Tc (INT) Tj ET 1 1 1 rg 72 202.8 468 171.12 re f 0 0 0 rg 139.68 338.4 0.24 0.48 re f 139.92 338.88 m 161.28 338.88 l 161.52 338.4 l 161.04 338.64 l 168 359.76 l 168 360 l 168.24 360 l 168.48 359.52 l 161.52 338.4 l 139.92 338.4 l h f 168.24 360 m 189.84 360 l 189.84 359.76 l 189.6 359.52 l 168.24 359.52 l h f 197.04 338.64 m 197.04 338.4 l 196.56 338.16 l 196.56 338.4 l h f 189.84 359.76 m 189.36 359.52 l 196.56 338.4 l 197.04 338.64 l h f 196.56 338.4 0.24 0.48 re f 196.8 338.88 m 217.92 338.88 l 218.16 338.4 l 217.68 338.64 l 224.88 359.76 l 224.88 360 l 225.12 360 l 225.36 359.52 l 218.16 338.4 l 196.8 338.4 l h f 225.12 360 m 246.48 360 l 246.48 359.76 l 246.24 359.52 l 225.12 359.52 l h f 253.68 338.64 m 253.68 338.4 l 253.2 338.16 l 253.2 338.4 l h f 246.48 359.76 m 246 359.52 l 253.2 338.4 l 253.68 338.64 l h f 253.2 338.4 0.24 0.48 re f 253.44 338.88 m 274.56 338.88 l 274.8 338.4 l 274.32 338.64 l 281.52 359.76 l 281.52 360 l 281.76 360 l 282 359.52 l 274.8 338.4 l 253.44 338.4 l h f 281.76 360 m 303.12 360 l 303.12 359.76 l 302.88 359.52 l 281.76 359.52 l h f 310.32 338.64 m 310.32 338.4 l 309.84 338.16 l 309.84 338.4 l h f 303.12 359.76 m 302.64 359.52 l 309.84 338.4 l 310.32 338.64 l h f 309.84 338.4 0.24 0.48 re f 310.08 338.88 m 331.44 338.88 l 331.68 338.4 l 331.2 338.64 l 338.16 359.76 l 338.16 360 l 338.4 360 l 338.64 359.52 l 331.68 338.4 l 310.08 338.4 l h f 338.4 360 m 360 360 l 360 359.76 l 359.76 359.52 l 338.4 359.52 l h f 366.96 338.64 m 366.96 338.4 l 366.48 338.16 l 366.48 338.4 l h f 360 359.76 m 359.52 359.52 l 366.48 338.4 l 366.96 338.64 l h f 366.48 338.4 0.24 0.48 re f 366.72 338.88 m 388.08 338.88 l 388.32 338.4 l 387.84 338.64 l 394.8 359.76 l 394.8 360 l 395.04 360 l 395.28 359.52 l 388.32 338.4 l 366.72 338.4 l h f 395.04 360 m 416.64 360 l 416.64 359.76 l 416.4 359.52 l 395.04 359.52 l h f 423.6 338.64 m 423.6 338.4 l 423.12 338.16 l 423.12 338.4 l h f 416.64 359.76 m 416.16 359.52 l 423.12 338.4 l 423.6 338.64 l h f 423.12 338.4 0.24 0.48 re f 423.36 338.88 m 444.72 338.88 l 444.96 338.4 l 444.48 338.64 l 451.68 359.76 l 451.68 360 l 451.92 360 l 452.16 359.52 l 444.96 338.4 l 423.36 338.4 l h f 451.92 360 m 473.28 360 l 473.28 359.76 l 473.04 359.52 l 451.92 359.52 l h f 480.48 338.64 m 480.48 338.4 l 480 338.16 l 480 338.4 l h f 473.28 359.76 m 472.8 359.52 l 480 338.4 l 480.48 338.64 l h f 480 338.4 0.24 0.48 re f 480.24 338.88 m 501.36 338.88 l 501.6 338.4 l 501.12 338.64 l 508.32 359.76 l 508.32 360 l 508.56 360 l 508.8 359.52 l 501.6 338.4 l 480.24 338.4 l h f 508.56 360 m 529.92 360 l 529.92 359.76 l 529.68 359.52 l 508.56 359.52 l h f 537.12 338.64 m 537.12 338.4 l 536.64 338.16 l 536.64 338.4 l h f 529.92 359.76 m 529.44 359.52 l 536.64 338.4 l 537.12 338.64 l h f BT 83.28 344.64 TD 0.1952 Tc (CLK) Tj ET 168.72 359.76 m 168.72 360.24 l 167.76 360.24 l 167.76 359.76 l h f 168.72 225.12 m 168.72 224.64 l 167.76 224.64 l 167.76 225.12 l h f 167.76 225.12 0.96 134.64 re f 282.24 359.76 m 282.24 360.24 l 281.28 360.24 l 281.28 359.76 l h f 282.24 225.12 m 282.24 224.64 l 281.28 224.64 l 281.28 225.12 l h f 281.28 225.12 0.96 134.64 re f 395.52 359.76 m 395.52 360.24 l 394.56 360.24 l 394.56 359.76 l h f 395.52 225.12 m 395.52 224.64 l 394.56 224.64 l 394.56 225.12 l h f 394.56 225.12 0.96 134.64 re f 509.04 359.76 m 509.04 360.24 l 508.08 360.24 l 508.08 359.76 l h f 509.04 218.16 m 509.04 217.68 l 508.08 217.68 l 508.08 218.16 l h f 508.08 218.16 0.96 141.6 re f 225.6 359.76 m 225.6 360.24 l 224.64 360.24 l 224.64 359.76 l h f 225.6 356.4 m 225.6 355.92 l 224.64 355.92 l 224.64 356.4 l h f 224.64 356.4 0.96 3.36 re f 225.6 349.92 m 225.6 350.4 l 224.64 350.4 l 224.64 349.92 l h f* 225.6 343.44 m 225.6 342.96 l 224.64 342.96 l 224.64 343.44 l h f* 224.64 343.44 0.96 6.48 re f* 225.6 336.96 m 225.6 337.44 l 224.64 337.44 l 224.64 336.96 l h f* 225.6 330.48 m 225.6 330 l 224.64 330 l 224.64 330.48 l h f* 224.64 330.48 0.96 6.48 re f* 225.6 324 m 225.6 324.48 l 224.64 324.48 l 224.64 324 l h f* 225.6 317.52 m 225.6 317.04 l 224.64 317.04 l 224.64 317.52 l h f* 224.64 317.52 0.96 6.48 re f* 225.6 311.04 m 225.6 311.52 l 224.64 311.52 l 224.64 311.04 l h f* 225.6 304.8 m 225.6 304.32 l 224.64 304.32 l 224.64 304.8 l h f* 224.64 304.8 0.96 6.24 re f* 225.6 298.32 m 225.6 298.8 l 224.64 298.8 l 224.64 298.32 l h f* 225.6 291.84 m 225.6 291.36 l 224.64 291.36 l 224.64 291.84 l h f* 224.64 291.84 0.96 6.48 re f* 225.6 285.36 m 225.6 285.84 l 224.64 285.84 l 224.64 285.36 l h f 225.6 281.76 m 225.6 281.28 l 224.64 281.28 l 224.64 281.76 l h f 224.64 281.76 0.96 3.6 re f 338.88 359.76 m 338.88 360.24 l 337.92 360.24 l 337.92 359.76 l h f 338.88 356.4 m 338.88 355.92 l 337.92 355.92 l 337.92 356.4 l h f 337.92 356.4 0.96 3.36 re f 338.88 349.92 m 338.88 350.4 l 337.92 350.4 l 337.92 349.92 l h f* 338.88 343.44 m 338.88 342.96 l 337.92 342.96 l 337.92 343.44 l h f* 337.92 343.44 0.96 6.48 re f* 338.88 336.96 m 338.88 337.44 l 337.92 337.44 l 337.92 336.96 l h f* 338.88 330.48 m 338.88 330 l 337.92 330 l 337.92 330.48 l h f* 337.92 330.48 0.96 6.48 re f* 338.88 324 m 338.88 324.48 l 337.92 324.48 l 337.92 324 l h f* 338.88 317.52 m 338.88 317.04 l 337.92 317.04 l 337.92 317.52 l h f* 337.92 317.52 0.96 6.48 re f* 338.88 311.04 m 338.88 311.52 l 337.92 311.52 l 337.92 311.04 l h f* 338.88 304.8 m 338.88 304.32 l 337.92 304.32 l 337.92 304.8 l h f* 337.92 304.8 0.96 6.24 re f* 338.88 298.32 m 338.88 298.8 l 337.92 298.8 l 337.92 298.32 l h f* 338.88 291.84 m 338.88 291.36 l 337.92 291.36 l 337.92 291.84 l h f* 337.92 291.84 0.96 6.48 re f* 338.88 285.36 m 338.88 285.84 l 337.92 285.84 l 337.92 285.36 l h f 338.88 281.76 m 338.88 281.28 l 337.92 281.28 l 337.92 281.76 l h f 337.92 281.76 0.96 3.6 re f 452.4 359.76 m 452.4 360.24 l 451.44 360.24 l 451.44 359.76 l h f 452.4 356.4 m 452.4 355.92 l 451.44 355.92 l 451.44 356.4 l h f 451.44 356.4 0.96 3.36 re f 452.4 349.92 m 452.4 350.4 l 451.44 350.4 l 451.44 349.92 l h f* 452.4 343.44 m 452.4 342.96 l 451.44 342.96 l 451.44 343.44 l h f* 451.44 343.44 0.96 6.48 re f* 452.4 336.96 m 452.4 337.44 l 451.44 337.44 l 451.44 336.96 l h f* 452.4 330.48 m 452.4 330 l 451.44 330 l 451.44 330.48 l h f* 451.44 330.48 0.96 6.48 re f* 452.4 324 m 452.4 324.48 l 451.44 324.48 l 451.44 324 l h f* 452.4 317.52 m 452.4 317.04 l 451.44 317.04 l 451.44 317.52 l h f* 451.44 317.52 0.96 6.48 re f* 452.4 311.04 m 452.4 311.52 l 451.44 311.52 l 451.44 311.04 l h f* 452.4 304.8 m 452.4 304.32 l 451.44 304.32 l 451.44 304.8 l h f* 451.44 304.8 0.96 6.24 re f* 452.4 298.32 m 452.4 298.8 l 451.44 298.8 l 451.44 298.32 l h f* 452.4 291.84 m 452.4 291.36 l 451.44 291.36 l 451.44 291.84 l h f* 451.44 291.84 0.96 6.48 re f* 452.4 285.36 m 452.4 285.84 l 451.44 285.84 l 451.44 285.36 l h f 452.4 281.76 m 452.4 281.28 l 451.44 281.28 l 451.44 281.76 l h f 451.44 281.76 0.96 3.6 re f 139.68 310.08 0.24 0.48 re f 139.92 310.56 m 168.48 310.56 l 168.48 310.32 l 175.68 288.96 l 175.44 288.72 l 175.44 289.2 l 225.12 289.2 l 225.36 288.72 l 175.2 288.72 l 168 310.08 l 168.48 310.32 l 168.24 310.08 l 139.92 310.08 l h f 224.88 288.96 m 231.84 310.32 l 231.84 310.56 l 232.08 310.56 l 232.32 310.08 l 225.36 288.72 l h f 253.44 310.08 0.24 0.48 re f 232.08 310.56 m 232.08 310.08 l 253.44 310.08 l 253.44 310.56 l h f 253.2 310.08 0.24 0.48 re f 253.44 310.56 m 282 310.56 l 282 310.32 l 288.96 288.96 l 288.72 288.72 l 288.72 289.2 l 338.4 289.2 l 338.64 288.72 l 288.48 288.72 l 281.52 310.08 l 282 310.32 l 281.76 310.08 l 253.44 310.08 l h f 338.16 288.96 m 345.36 310.32 l 345.36 310.56 l 345.6 310.56 l 345.84 310.08 l 338.64 288.72 l h f 366.72 310.08 0.24 0.48 re f 345.6 310.56 m 345.6 310.08 l 366.72 310.08 l 366.72 310.56 l h f 366.48 310.08 0.24 0.48 re f 366.72 310.56 m 395.28 310.56 l 395.28 310.32 l 402.48 288.96 l 402.24 288.72 l 402.24 289.2 l 451.92 289.2 l 452.16 288.72 l 402 288.72 l 394.8 310.08 l 395.28 310.32 l 395.04 310.08 l 366.72 310.08 l h f 451.68 288.96 m 458.64 310.32 l 458.64 310.56 l 458.88 310.56 l 459.12 310.08 l 452.16 288.72 l h f 480.24 310.08 0.24 0.48 re f 458.88 310.56 m 458.88 310.08 l 480.24 310.08 l 480.24 310.56 l h f 480 310.08 0.24 0.48 re f 480.24 310.56 m 508.8 310.56 l 508.8 310.32 l 508.56 310.08 l 480.24 310.08 l h f 508.8 310.32 m 522.96 281.76 l 522.72 281.52 l 522.48 281.52 l 508.32 310.08 l h f 536.88 281.52 0.24 0.48 re f 522.72 282 m 522.72 281.52 l 536.88 281.52 l 536.88 282 l h f BT 90.48 295.2 TD 0.1236 Tc (T2) Tj ET 179.76 239.28 m 179.76 235.92 l 179.04 236.16 l 169.92 238.8 l 168.24 239.28 l 169.92 239.76 l 179.04 242.4 l 179.76 242.64 l 179.76 241.92 l 179.28 241.44 l 170.16 238.8 l 169.92 239.76 l 170.16 239.76 l 179.28 237.12 l 179.04 236.16 l 178.8 236.64 l 178.8 239.28 l h f 179.76 241.92 m 179.76 239.28 l 178.8 239.28 l 178.8 241.92 l h f 179.28 239.28 m 179.28 236.64 l 170.16 239.28 l 179.28 241.92 l h f* 270.24 239.28 m 270.24 242.64 l 270.96 242.4 l 280.08 239.76 l 281.76 239.28 l 280.08 238.8 l 270.96 236.16 l 270.24 235.92 l 270.24 236.64 l 270.72 237.12 l 279.84 239.76 l 280.08 238.8 l 279.84 238.8 l 270.72 241.44 l 270.96 242.4 l 271.2 241.92 l 271.2 239.28 l h f 270.24 236.64 m 270.24 239.28 l 271.2 239.28 l 271.2 236.64 l h f 270.72 239.28 m 270.72 241.92 l 279.84 239.28 l 270.72 236.64 l h f* 179.52 239.04 0.24 0.48 re f 270.24 239.04 0.24 0.48 re f 179.76 239.52 m 179.76 239.04 l 270.24 239.04 l 270.24 239.52 l h f 293.28 239.28 m 293.28 235.92 l 292.56 236.16 l 283.2 238.8 l 281.52 239.28 l 283.2 239.76 l 292.56 242.4 l 293.28 242.64 l 293.28 241.92 l 292.8 241.44 l 283.44 238.8 l 283.2 239.76 l 283.44 239.76 l 292.8 237.12 l 292.56 236.16 l 292.32 236.64 l 292.32 239.28 l h f 293.28 241.92 m 293.28 239.28 l 292.32 239.28 l 292.32 241.92 l h f 292.8 239.28 m 292.8 236.64 l 283.44 239.28 l 292.8 241.92 l h f* 383.52 239.28 m 383.52 242.64 l 384.24 242.4 l 393.6 239.76 l 395.28 239.28 l 393.6 238.8 l 384.24 236.16 l 383.52 235.92 l 383.52 236.64 l 384 237.12 l 393.36 239.76 l 393.6 238.8 l 393.36 238.8 l 384 241.44 l 384.24 242.4 l 384.48 241.92 l 384.48 239.28 l h f 383.52 236.64 m 383.52 239.28 l 384.48 239.28 l 384.48 236.64 l h f 384 239.28 m 384 241.92 l 393.36 239.28 l 384 236.64 l h f* 293.04 239.04 0.24 0.48 re f 383.52 239.04 0.24 0.48 re f 293.28 239.52 m 293.28 239.04 l 383.52 239.04 l 383.52 239.52 l h f 406.56 239.28 m 406.56 235.92 l 405.84 236.16 l 396.72 238.8 l 395.04 239.28 l 396.72 239.76 l 405.84 242.4 l 406.56 242.64 l 406.56 241.92 l 406.08 241.44 l 396.96 238.8 l 396.72 239.76 l 396.96 239.76 l 406.08 237.12 l 405.84 236.16 l 405.6 236.64 l 405.6 239.28 l h f 406.56 241.92 m 406.56 239.28 l 405.6 239.28 l 405.6 241.92 l h f 406.08 239.28 m 406.08 236.64 l 396.96 239.28 l 406.08 241.92 l h f* 497.04 239.28 m 497.04 242.64 l 497.76 242.4 l 506.88 239.76 l 508.56 239.28 l 506.88 238.8 l 497.76 236.16 l 497.04 235.92 l 497.04 236.64 l 497.52 237.12 l 506.64 239.76 l 506.88 238.8 l 506.64 238.8 l 497.52 241.44 l 497.76 242.4 l 498 241.92 l 498 239.28 l h f 497.04 236.64 m 497.04 239.28 l 498 239.28 l 498 236.64 l h f 497.52 239.28 m 497.52 241.92 l 506.64 239.28 l 497.52 236.64 l h f* 406.32 239.04 0.24 0.48 re f 497.04 239.04 0.24 0.48 re f 406.56 239.52 m 406.56 239.04 l 497.04 239.04 l 497.04 239.52 l h f BT 217.68 241.44 TD 0.1152 Tc (M1) Tj 113.76 0 TD 0.2352 Tc (M2) Tj 113.04 0 TD 0.1152 Tc (M3) Tj ET endstream endobj 36 0 obj 25159 endobj 34 0 obj << /Type /Page /Parent 28 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 35 0 R >> endobj 38 0 obj << /Length 39 0 R >> stream BT 77.76 712.08 TD 0 0 0 rg /F1 12 Tf 0.0592 Tc -0.2152 Tw (In the first half of a M cycle \(T2 = 0\), the program counter is placed on the memory address bus;) Tj -5.76 -14.16 TD 0.0954 Tc 0.2286 Tw (this is always a read cycle. In the second half of a M cycle, the operand address is placed on the) Tj 0 -13.92 TD 0.0905 Tc -0.1933 Tw (memory address bus; this could be a read cycle, a write cycle, or no cycle:) Tj 5.76 -19.92 TD 0 Tc 0 Tw ( ) Tj 0 -332.88 TD 0.0557 Tc 2.8385 Tw (The opcode is clocked again at the end of an M cycle, so that, from the perspective of) Tj -5.76 -14.16 TD 0.0623 Tc 0.7327 Tw (opcode_decoder and data_core, all signals change at the end of a M cycle, an the system looks) Tj 0 -13.92 TD 0.0607 Tc -0.4419 Tw (like running at the rate of T2, rather than CLK: Therefore, with the exception of the signals above,) Tj T* 0.0842 Tc 0.1558 Tw (all signals of the CPU are clocked at the end of T2 \(they are still clocked with CLK, but only on) Tj 0 -14.16 TD 0.0929 Tc -0.2129 Tw (every second cycle of CLK when T2 = 1\).) Tj 5.76 -19.92 TD 0 Tc 0 Tw ( ) Tj ET 1 1 1 rg 72 347.04 468 312.96 re f 0 0 0 rg 139.68 624.24 0.24 0.48 re f 139.92 624.72 m 161.28 624.72 l 161.52 624.24 l 161.04 624.48 l 168 645.84 l 168 646.08 l 168.24 646.08 l 168.48 645.6 l 161.52 624.24 l 139.92 624.24 l h f 168.24 646.08 m 189.84 646.08 l 189.84 645.84 l 189.6 645.6 l 168.24 645.6 l h f 197.04 624.48 m 197.04 624.24 l 196.56 624 l 196.56 624.24 l h f 189.84 645.84 m 189.36 645.6 l 196.56 624.24 l 197.04 624.48 l h f 196.56 624.24 0.24 0.48 re f 196.8 624.72 m 217.92 624.72 l 218.16 624.24 l 217.68 624.48 l 224.88 645.84 l 224.88 646.08 l 225.12 646.08 l 225.36 645.6 l 218.16 624.24 l 196.8 624.24 l h f 225.12 646.08 m 246.48 646.08 l 246.48 645.84 l 246.24 645.6 l 225.12 645.6 l h f 253.68 624.48 m 253.68 624.24 l 253.2 624 l 253.2 624.24 l h f 246.48 645.84 m 246 645.6 l 253.2 624.24 l 253.68 624.48 l h f 253.2 624.24 0.24 0.48 re f 253.44 624.72 m 274.56 624.72 l 274.8 624.24 l 274.32 624.48 l 281.52 645.84 l 281.52 646.08 l 281.76 646.08 l 282 645.6 l 274.8 624.24 l 253.44 624.24 l h f 281.76 646.08 m 303.12 646.08 l 303.12 645.84 l 302.88 645.6 l 281.76 645.6 l h f 310.32 624.48 m 310.32 624.24 l 309.84 624 l 309.84 624.24 l h f 303.12 645.84 m 302.64 645.6 l 309.84 624.24 l 310.32 624.48 l h f 309.84 624.24 0.24 0.48 re f 310.08 624.72 m 331.44 624.72 l 331.68 624.24 l 331.2 624.48 l 338.16 645.84 l 338.16 646.08 l 338.4 646.08 l 338.64 645.6 l 331.68 624.24 l 310.08 624.24 l h f 338.4 646.08 m 360 646.08 l 360 645.84 l 359.76 645.6 l 338.4 645.6 l h f 366.96 624.48 m 366.96 624.24 l 366.48 624 l 366.48 624.24 l h f 360 645.84 m 359.52 645.6 l 366.48 624.24 l 366.96 624.48 l h f 366.48 624.24 0.24 0.48 re f 366.72 624.72 m 388.08 624.72 l 388.32 624.24 l 387.84 624.48 l 394.8 645.84 l 394.8 646.08 l 395.04 646.08 l 395.28 645.6 l 388.32 624.24 l 366.72 624.24 l h f 395.04 646.08 m 416.64 646.08 l 416.64 645.84 l 416.4 645.6 l 395.04 645.6 l h f 423.6 624.48 m 423.6 624.24 l 423.12 624 l 423.12 624.24 l h f 416.64 645.84 m 416.16 645.6 l 423.12 624.24 l 423.6 624.48 l h f 423.12 624.24 0.24 0.48 re f 423.36 624.72 m 444.72 624.72 l 444.96 624.24 l 444.48 624.48 l 451.68 645.84 l 451.68 646.08 l 451.92 646.08 l 452.16 645.6 l 444.96 624.24 l 423.36 624.24 l h f 451.92 646.08 m 473.28 646.08 l 473.28 645.84 l 473.04 645.6 l 451.92 645.6 l h f 480.48 624.48 m 480.48 624.24 l 480 624 l 480 624.24 l h f 473.28 645.84 m 472.8 645.6 l 480 624.24 l 480.48 624.48 l h f 480 624.24 0.24 0.48 re f 480.24 624.72 m 501.36 624.72 l 501.6 624.24 l 501.12 624.48 l 508.32 645.84 l 508.32 646.08 l 508.56 646.08 l 508.8 645.6 l 501.6 624.24 l 480.24 624.24 l h f 508.56 646.08 m 529.92 646.08 l 529.92 645.84 l 529.68 645.6 l 508.56 645.6 l h f 537.12 624.48 m 537.12 624.24 l 536.64 624 l 536.64 624.24 l h f 529.92 645.84 m 529.44 645.6 l 536.64 624.24 l 537.12 624.48 l h f BT 83.28 630.72 TD /F0 9.84 Tf 0.1952 Tc (CLK) Tj ET 168.72 645.84 m 168.72 646.32 l 167.76 646.32 l 167.76 645.84 l h f 168.72 397.68 m 168.72 397.2 l 167.76 397.2 l 167.76 397.68 l h f 167.76 397.68 0.96 248.16 re f 282.24 645.84 m 282.24 646.32 l 281.28 646.32 l 281.28 645.84 l h f 282.24 397.68 m 282.24 397.2 l 281.28 397.2 l 281.28 397.68 l h f 281.28 397.68 0.96 248.16 re f 395.52 645.84 m 395.52 646.32 l 394.56 646.32 l 394.56 645.84 l h f 395.52 397.68 m 395.52 397.2 l 394.56 397.2 l 394.56 397.68 l h f 394.56 397.68 0.96 248.16 re f 509.04 645.84 m 509.04 646.32 l 508.08 646.32 l 508.08 645.84 l h f 509.04 397.68 m 509.04 397.2 l 508.08 397.2 l 508.08 397.68 l h f 508.08 397.68 0.96 248.16 re f 225.6 645.84 m 225.6 646.32 l 224.64 646.32 l 224.64 645.84 l h f 225.6 642.24 m 225.6 641.76 l 224.64 641.76 l 224.64 642.24 l h f 224.64 642.24 0.96 3.6 re f 225.6 635.28 m 225.6 635.76 l 224.64 635.76 l 224.64 635.28 l h f* 225.6 628.08 m 225.6 627.6 l 224.64 627.6 l 224.64 628.08 l h f* 224.64 628.08 0.96 7.2 re f* 225.6 621.12 m 225.6 621.6 l 224.64 621.6 l 224.64 621.12 l h f* 225.6 613.92 m 225.6 613.44 l 224.64 613.44 l 224.64 613.92 l h f* 224.64 613.92 0.96 7.2 re f* 225.6 606.96 m 225.6 607.44 l 224.64 607.44 l 224.64 606.96 l h f* 225.6 599.76 m 225.6 599.28 l 224.64 599.28 l 224.64 599.76 l h f* 224.64 599.76 0.96 7.2 re f* 225.6 592.8 m 225.6 593.28 l 224.64 593.28 l 224.64 592.8 l h f* 225.6 585.6 m 225.6 585.12 l 224.64 585.12 l 224.64 585.6 l h f* 224.64 585.6 0.96 7.2 re f* 225.6 578.4 m 225.6 578.88 l 224.64 578.88 l 224.64 578.4 l h f* 225.6 571.44 m 225.6 570.96 l 224.64 570.96 l 224.64 571.44 l h f* 224.64 571.44 0.96 6.96 re f* 225.6 564.24 m 225.6 564.72 l 224.64 564.72 l 224.64 564.24 l h f* 225.6 557.28 m 225.6 556.8 l 224.64 556.8 l 224.64 557.28 l h f* 224.64 557.28 0.96 6.96 re f* 225.6 550.08 m 225.6 550.56 l 224.64 550.56 l 224.64 550.08 l h f* 225.6 543.12 m 225.6 542.64 l 224.64 542.64 l 224.64 543.12 l h f* 224.64 543.12 0.96 6.96 re f* 225.6 535.92 m 225.6 536.4 l 224.64 536.4 l 224.64 535.92 l h f* 225.6 528.96 m 225.6 528.48 l 224.64 528.48 l 224.64 528.96 l h f* 224.64 528.96 0.96 6.96 re f* 225.6 521.76 m 225.6 522.24 l 224.64 522.24 l 224.64 521.76 l h f* 225.6 514.8 m 225.6 514.32 l 224.64 514.32 l 224.64 514.8 l h f* 224.64 514.8 0.96 6.96 re f* 225.6 507.6 m 225.6 508.08 l 224.64 508.08 l 224.64 507.6 l h f 225.6 504 m 225.6 503.52 l 224.64 503.52 l 224.64 504 l h f 224.64 504 0.96 3.6 re f 338.88 645.84 m 338.88 646.32 l 337.92 646.32 l 337.92 645.84 l h f 338.88 642.24 m 338.88 641.76 l 337.92 641.76 l 337.92 642.24 l h f 337.92 642.24 0.96 3.6 re f 338.88 635.28 m 338.88 635.76 l 337.92 635.76 l 337.92 635.28 l h f* 338.88 628.08 m 338.88 627.6 l 337.92 627.6 l 337.92 628.08 l h f* 337.92 628.08 0.96 7.2 re f* 338.88 621.12 m 338.88 621.6 l 337.92 621.6 l 337.92 621.12 l h f* 338.88 613.92 m 338.88 613.44 l 337.92 613.44 l 337.92 613.92 l h f* 337.92 613.92 0.96 7.2 re f* 338.88 606.96 m 338.88 607.44 l 337.92 607.44 l 337.92 606.96 l h f* 338.88 599.76 m 338.88 599.28 l 337.92 599.28 l 337.92 599.76 l h f* 337.92 599.76 0.96 7.2 re f* 338.88 592.8 m 338.88 593.28 l 337.92 593.28 l 337.92 592.8 l h f* 338.88 585.6 m 338.88 585.12 l 337.92 585.12 l 337.92 585.6 l h f* 337.92 585.6 0.96 7.2 re f* 338.88 578.4 m 338.88 578.88 l 337.92 578.88 l 337.92 578.4 l h f* 338.88 571.44 m 338.88 570.96 l 337.92 570.96 l 337.92 571.44 l h f* 337.92 571.44 0.96 6.96 re f* 338.88 564.24 m 338.88 564.72 l 337.92 564.72 l 337.92 564.24 l h f* 338.88 557.28 m 338.88 556.8 l 337.92 556.8 l 337.92 557.28 l h f* 337.92 557.28 0.96 6.96 re f* 338.88 550.08 m 338.88 550.56 l 337.92 550.56 l 337.92 550.08 l h f* 338.88 543.12 m 338.88 542.64 l 337.92 542.64 l 337.92 543.12 l h f* 337.92 543.12 0.96 6.96 re f* 338.88 535.92 m 338.88 536.4 l 337.92 536.4 l 337.92 535.92 l h f* 338.88 528.96 m 338.88 528.48 l 337.92 528.48 l 337.92 528.96 l h f* 337.92 528.96 0.96 6.96 re f* 338.88 521.76 m 338.88 522.24 l 337.92 522.24 l 337.92 521.76 l h f* 338.88 514.8 m 338.88 514.32 l 337.92 514.32 l 337.92 514.8 l h f* 337.92 514.8 0.96 6.96 re f* 338.88 507.6 m 338.88 508.08 l 337.92 508.08 l 337.92 507.6 l h f 338.88 504 m 338.88 503.52 l 337.92 503.52 l 337.92 504 l h f 337.92 504 0.96 3.6 re f 452.4 645.84 m 452.4 646.32 l 451.44 646.32 l 451.44 645.84 l h f 452.4 642.24 m 452.4 641.76 l 451.44 641.76 l 451.44 642.24 l h f 451.44 642.24 0.96 3.6 re f 452.4 635.28 m 452.4 635.76 l 451.44 635.76 l 451.44 635.28 l h f* 452.4 628.08 m 452.4 627.6 l 451.44 627.6 l 451.44 628.08 l h f* 451.44 628.08 0.96 7.2 re f* 452.4 621.12 m 452.4 621.6 l 451.44 621.6 l 451.44 621.12 l h f* 452.4 613.92 m 452.4 613.44 l 451.44 613.44 l 451.44 613.92 l h f* 451.44 613.92 0.96 7.2 re f* 452.4 606.96 m 452.4 607.44 l 451.44 607.44 l 451.44 606.96 l h f* 452.4 599.76 m 452.4 599.28 l 451.44 599.28 l 451.44 599.76 l h f* 451.44 599.76 0.96 7.2 re f* 452.4 592.8 m 452.4 593.28 l 451.44 593.28 l 451.44 592.8 l h f* 452.4 585.6 m 452.4 585.12 l 451.44 585.12 l 451.44 585.6 l h f* 451.44 585.6 0.96 7.2 re f* 452.4 578.4 m 452.4 578.88 l 451.44 578.88 l 451.44 578.4 l h f* 452.4 571.44 m 452.4 570.96 l 451.44 570.96 l 451.44 571.44 l h f* 451.44 571.44 0.96 6.96 re f* 452.4 564.24 m 452.4 564.72 l 451.44 564.72 l 451.44 564.24 l h f* 452.4 557.28 m 452.4 556.8 l 451.44 556.8 l 451.44 557.28 l h f* 451.44 557.28 0.96 6.96 re f* 452.4 550.08 m 452.4 550.56 l 451.44 550.56 l 451.44 550.08 l h f* 452.4 543.12 m 452.4 542.64 l 451.44 542.64 l 451.44 543.12 l h f* 451.44 543.12 0.96 6.96 re f* 452.4 535.92 m 452.4 536.4 l 451.44 536.4 l 451.44 535.92 l h f* 452.4 528.96 m 452.4 528.48 l 451.44 528.48 l 451.44 528.96 l h f* 451.44 528.96 0.96 6.96 re f* 452.4 521.76 m 452.4 522.24 l 451.44 522.24 l 451.44 521.76 l h f* 452.4 514.8 m 452.4 514.32 l 451.44 514.32 l 451.44 514.8 l h f* 451.44 514.8 0.96 6.96 re f* 452.4 507.6 m 452.4 508.08 l 451.44 508.08 l 451.44 507.6 l h f 452.4 504 m 452.4 503.52 l 451.44 503.52 l 451.44 504 l h f 451.44 504 0.96 3.6 re f 139.68 595.92 0.24 0.48 re f 139.92 596.4 m 168.48 596.4 l 168.48 596.16 l 175.68 575.04 l 175.44 574.8 l 175.44 575.28 l 225.12 575.28 l 225.36 574.8 l 175.2 574.8 l 168 595.92 l 168.48 596.16 l 168.24 595.92 l 139.92 595.92 l h f 224.88 575.04 m 231.84 596.16 l 231.84 596.4 l 232.08 596.4 l 232.32 595.92 l 225.36 574.8 l h f 253.44 595.92 0.24 0.48 re f 232.08 596.4 m 232.08 595.92 l 253.44 595.92 l 253.44 596.4 l h f 253.2 595.92 0.24 0.48 re f 253.44 596.4 m 282 596.4 l 282 596.16 l 288.96 575.04 l 288.72 574.8 l 288.72 575.28 l 338.4 575.28 l 338.64 574.8 l 288.48 574.8 l 281.52 595.92 l 282 596.16 l 281.76 595.92 l 253.44 595.92 l h f 338.16 575.04 m 345.36 596.16 l 345.36 596.4 l 345.6 596.4 l 345.84 595.92 l 338.64 574.8 l h f 366.72 595.92 0.24 0.48 re f 345.6 596.4 m 345.6 595.92 l 366.72 595.92 l 366.72 596.4 l h f 366.48 595.92 0.24 0.48 re f 366.72 596.4 m 395.28 596.4 l 395.28 596.16 l 402.48 575.04 l 402.24 574.8 l 402.24 575.28 l 451.92 575.28 l 452.16 574.8 l 402 574.8 l 394.8 595.92 l 395.28 596.16 l 395.04 595.92 l 366.72 595.92 l h f 451.68 575.04 m 458.64 596.16 l 458.64 596.4 l 458.88 596.4 l 459.12 595.92 l 452.16 574.8 l h f 480.24 595.92 0.24 0.48 re f 458.88 596.4 m 458.88 595.92 l 480.24 595.92 l 480.24 596.4 l h f 480 595.92 0.24 0.48 re f 480.24 596.4 m 508.56 596.4 l 508.8 596.16 l 508.56 595.92 l 480.24 595.92 l h f 508.8 596.16 m 522.96 567.84 l 522.72 567.6 l 522.48 567.6 l 508.32 595.92 l h f 536.88 567.6 0.24 0.48 re f 522.72 568.08 m 522.72 567.6 l 536.88 567.6 l 536.88 568.08 l h f BT 83.28 581.04 TD 0.1236 Tc (T2) Tj ET 168 532.56 m 168 532.32 l 168.48 532.08 l 168.48 532.32 l h f 168 532.56 m 175.2 553.68 l 175.2 553.92 l 225.36 553.92 l 225.36 553.68 l 225.12 553.44 l 175.44 553.44 l 175.44 553.92 l 175.68 553.44 l 168.48 532.32 l h f 225.36 553.68 m 232.32 525.36 l 232.08 525.12 l 231.84 525.12 l 231.84 525.36 l 224.88 553.68 l h f 281.76 525.12 0.24 0.48 re f 232.08 525.6 m 232.08 525.12 l 281.76 525.12 l 281.76 525.6 l h f 168.48 553.68 m 168.48 553.92 l 168 553.92 l 168 553.68 l h f 168.48 553.68 m 175.68 525.36 l 175.44 525.12 l 175.44 525.6 l 225.12 525.6 l 225.36 525.36 l 225.36 525.12 l 175.2 525.12 l 175.2 525.36 l 168 553.68 l h f 224.88 525.36 m 231.84 553.68 l 231.84 553.92 l 232.08 553.92 l 232.32 553.68 l 225.36 525.36 l h f 281.76 553.44 0.24 0.48 re f 232.08 553.92 m 232.08 553.44 l 281.76 553.44 l 281.76 553.92 l h f 281.52 532.56 m 281.52 532.32 l 282 532.08 l 282 532.32 l h f 281.52 532.56 m 288.48 553.68 l 288.48 553.92 l 338.64 553.92 l 338.64 553.68 l 338.4 553.44 l 288.72 553.44 l 288.72 553.92 l 288.96 553.44 l 282 532.32 l h f 338.64 553.68 m 345.84 525.36 l 345.6 525.12 l 345.36 525.12 l 345.36 525.36 l 338.16 553.68 l h f 395.04 525.12 0.24 0.48 re f 345.6 525.6 m 345.6 525.12 l 395.04 525.12 l 395.04 525.6 l h f 282 553.68 m 282 553.92 l 281.52 553.92 l 281.52 553.68 l h f 282 553.68 m 288.96 525.36 l 288.72 525.12 l 288.72 525.6 l 338.4 525.6 l 338.64 525.36 l 338.64 525.12 l 288.48 525.12 l 288.48 525.36 l 281.52 553.68 l h f 338.16 525.36 m 345.36 553.68 l 345.36 553.92 l 345.6 553.92 l 345.84 553.68 l 338.64 525.36 l h f 395.04 553.44 0.24 0.48 re f 345.6 553.92 m 345.6 553.44 l 395.04 553.44 l 395.04 553.92 l h f BT 471.12 485.52 TD 0.1114 Tc (\(PC3\)) Tj ET 394.8 532.56 m 394.8 532.32 l 395.28 532.08 l 395.28 532.32 l h f 394.8 532.56 m 402 553.68 l 402 553.92 l 452.16 553.92 l 452.16 553.68 l 451.92 553.44 l 402.24 553.44 l 402.24 553.92 l 402.48 553.44 l 395.28 532.32 l h f 452.16 553.68 m 459.12 525.36 l 458.88 525.12 l 458.64 525.12 l 458.64 525.36 l 451.68 553.68 l h f 508.56 525.12 0.24 0.48 re f 458.88 525.6 m 458.88 525.12 l 508.56 525.12 l 508.56 525.6 l h f 395.28 553.68 m 395.28 553.92 l 394.8 553.92 l 394.8 553.68 l h f 395.28 553.68 m 402.48 525.36 l 402.24 525.12 l 402.24 525.6 l 451.92 525.6 l 452.16 525.36 l 452.16 525.12 l 402 525.12 l 402 525.36 l 394.8 553.68 l h f 451.68 525.36 m 458.64 553.68 l 458.64 553.92 l 458.88 553.92 l 459.12 553.68 l 452.16 525.36 l h f 508.56 553.44 0.24 0.48 re f 458.88 553.92 m 458.88 553.44 l 508.56 553.44 l 508.56 553.92 l h f 168.24 553.44 0.24 0.48 re f 139.68 553.44 0.24 0.48 re f 168.24 553.44 m 168.24 553.92 l 139.92 553.92 l 139.92 553.44 l h f 168.24 525.12 0.24 0.48 re f 139.68 525.12 0.24 0.48 re f 168.24 525.12 m 168.24 525.6 l 139.92 525.6 l 139.92 525.12 l h f 515.28 525.36 m 515.28 525.12 l 515.76 525.12 l 515.76 525.36 l h f 508.32 553.68 m 508.32 553.92 l 508.8 553.92 l 508.8 553.68 l h f 515.28 525.36 m 515.76 525.36 l 508.8 553.68 l 508.32 553.68 l h f 508.32 525.36 m 508.32 525.12 l 508.8 525.12 l 508.8 525.36 l h f 515.28 553.68 m 515.28 553.92 l 515.76 553.92 l 515.76 553.68 l h f 508.32 525.36 m 508.8 525.36 l 515.76 553.68 l 515.28 553.68 l h f 536.88 553.44 0.24 0.48 re f 515.28 553.44 0.24 0.48 re f 536.88 553.44 m 536.88 553.92 l 515.52 553.92 l 515.52 553.44 l h f 536.88 525.12 0.24 0.48 re f 515.28 525.12 0.24 0.48 re f 536.88 525.12 m 536.88 525.6 l 515.52 525.6 l 515.52 525.12 l h f 225.36 504 m 225.36 504.24 l 224.88 504.24 l 224.88 504 l h f 225.36 504 m 224.88 504 l 231.84 475.68 l 231.84 475.44 l 232.08 475.44 l 232.32 475.68 l h f 338.4 475.44 0.24 0.48 re f 232.08 475.92 m 232.08 475.44 l 338.4 475.44 l 338.4 475.92 l h f 224.88 475.68 m 224.88 475.44 l 225.36 475.44 l 225.36 475.68 l h f 224.88 475.68 m 225.36 475.68 l 232.32 504 l 232.08 504.24 l 231.84 504.24 l 231.84 504 l h f 338.4 503.76 0.24 0.48 re f 232.08 504.24 m 232.08 503.76 l 338.4 503.76 l 338.4 504.24 l h f 338.64 504 m 338.64 504.24 l 338.16 504.24 l 338.16 504 l h f 338.64 504 m 338.16 504 l 345.36 475.68 l 345.36 475.44 l 345.6 475.44 l 345.84 475.68 l h f 451.92 475.44 0.24 0.48 re f 345.6 475.92 m 345.6 475.44 l 451.92 475.44 l 451.92 475.92 l h f 338.16 475.68 m 338.16 475.44 l 338.64 475.44 l 338.64 475.68 l h f 338.16 475.68 m 338.64 475.68 l 345.84 504 l 345.6 504.24 l 345.36 504.24 l 345.36 504 l h f 451.92 503.76 0.24 0.48 re f 345.6 504.24 m 345.6 503.76 l 451.92 503.76 l 451.92 504.24 l h f 452.16 504 m 452.16 504.24 l 451.68 504.24 l 451.68 504 l h f 452.16 504 m 451.68 504 l 458.64 475.68 l 458.64 475.44 l 458.88 475.44 l 459.12 475.68 l h f 536.88 475.44 0.24 0.48 re f 458.88 475.92 m 458.88 475.44 l 536.88 475.44 l 536.88 475.92 l h f 451.68 475.68 m 451.68 475.44 l 452.16 475.44 l 452.16 475.68 l h f 451.68 475.68 m 452.16 475.68 l 459.12 504 l 458.88 504.24 l 458.64 504.24 l 458.64 504 l h f 536.88 503.76 0.24 0.48 re f 458.88 504.24 m 458.88 503.76 l 536.88 503.76 l 536.88 504.24 l h f 225.12 503.76 0.24 0.48 re f 139.68 503.76 0.24 0.48 re f 225.12 503.76 m 225.12 504.24 l 139.92 504.24 l 139.92 503.76 l h f 225.12 475.44 0.24 0.48 re f 139.68 475.44 0.24 0.48 re f 225.12 475.44 m 225.12 475.92 l 139.92 475.92 l 139.92 475.44 l h f 282 454.56 m 282 454.8 l 281.52 454.8 l 281.52 454.56 l h f 282 454.56 m 281.52 454.56 l 288.48 426.24 l 288.48 426 l 288.72 426 l 288.96 426.24 l h f 395.04 426 0.24 0.48 re f 288.72 426.48 m 288.72 426 l 395.04 426 l 395.04 426.48 l h f 281.52 426.24 m 281.52 426 l 282 426 l 282 426.24 l h f 281.52 426.24 m 282 426.24 l 288.96 454.56 l 288.72 454.8 l 288.48 454.8 l 288.48 454.56 l h f 395.04 454.32 0.24 0.48 re f 288.72 454.8 m 288.72 454.32 l 395.04 454.32 l 395.04 454.8 l h f 395.28 454.56 m 395.28 454.8 l 394.8 454.8 l 394.8 454.56 l h f 395.28 454.56 m 394.8 454.56 l 402 426.24 l 402 426 l 402.24 426 l 402.48 426.24 l h f 508.56 426 0.24 0.48 re f 402.24 426.48 m 402.24 426 l 508.56 426 l 508.56 426.48 l h f 394.8 426.24 m 394.8 426 l 395.28 426 l 395.28 426.24 l h f 394.8 426.24 m 395.28 426.24 l 402.48 454.56 l 402.24 454.8 l 402 454.8 l 402 454.56 l h f 508.56 454.32 0.24 0.48 re f 402.24 454.8 m 402.24 454.32 l 508.56 454.32 l 508.56 454.8 l h f 168.48 454.56 m 168.48 454.8 l 168 454.8 l 168 454.56 l h f 168.48 454.56 m 168 454.56 l 175.2 426.24 l 175.2 426 l 175.44 426 l 175.68 426.24 l h f 281.76 426 0.24 0.48 re f 175.44 426.48 m 175.44 426 l 281.76 426 l 281.76 426.48 l h f 168 426.24 m 168 426 l 168.48 426 l 168.48 426.24 l h f 168 426.24 m 168.48 426.24 l 175.68 454.56 l 175.44 454.8 l 175.2 454.8 l 175.2 454.56 l h f 281.76 454.32 0.24 0.48 re f 175.44 454.8 m 175.44 454.32 l 281.76 454.32 l 281.76 454.8 l h f 168.24 454.32 0.24 0.48 re f 139.68 454.32 0.24 0.48 re f 168.24 454.32 m 168.24 454.8 l 139.92 454.8 l 139.92 454.32 l h f 168.24 426 0.24 0.48 re f 139.68 426 0.24 0.48 re f 168.24 426 m 168.24 426.48 l 139.92 426.48 l 139.92 426 l h f 515.28 426.24 m 515.28 426 l 515.76 426 l 515.76 426.24 l h f 508.32 454.56 m 508.32 454.8 l 508.8 454.8 l 508.8 454.56 l h f 515.28 426.24 m 515.76 426.24 l 508.8 454.56 l 508.32 454.56 l h f 508.32 426.24 m 508.32 426 l 508.8 426 l 508.8 426.24 l h f 515.28 454.56 m 515.28 454.8 l 515.76 454.8 l 515.76 454.56 l h f 508.32 426.24 m 508.8 426.24 l 515.76 454.56 l 515.28 454.56 l h f 536.88 454.32 0.24 0.48 re f 515.28 454.32 0.24 0.48 re f 536.88 454.32 m 536.88 454.8 l 515.52 454.8 l 515.52 454.32 l h f 536.88 426 0.24 0.48 re f 515.28 426 0.24 0.48 re f 536.88 426 m 536.88 426.48 l 515.52 426.48 l 515.52 426 l h f BT 304.56 535.2 TD 0.1904 Tc (PC2) Tj 113.28 0 TD 0.1104 Tc (PC3) Tj -226.8 0 TD (PC1) Tj 53.28 -49.68 TD 0.1114 Tc (\(PC1\)) Tj 113.52 0 TD (\(PC2\)) Tj 52.56 -49.68 TD 0.0752 Tc (\(ADR2\)) Tj -113.52 0 TD 0.1152 Tc (\(ADR1\)) Tj 173.52 99.36 TD 0.1164 Tc (ADR3) Tj -226.8 0 TD (ADR1) Tj 113.28 0 TD (ADR2) Tj ET 282 397.68 m 282 397.92 l 281.52 397.92 l 281.52 397.68 l h f 282 397.68 m 281.52 397.68 l 288.48 369.36 l 288.48 369.12 l 288.72 369.12 l 288.96 369.36 l h f 395.04 369.12 0.24 0.48 re f 288.72 369.6 m 288.72 369.12 l 395.04 369.12 l 395.04 369.6 l h f 281.52 369.36 m 281.52 369.12 l 282 369.12 l 282 369.36 l h f 281.52 369.36 m 282 369.36 l 288.96 397.68 l 288.72 397.92 l 288.48 397.92 l 288.48 397.68 l h f 395.04 397.44 0.24 0.48 re f 288.72 397.92 m 288.72 397.44 l 395.04 397.44 l 395.04 397.92 l h f 395.28 397.68 m 395.28 397.92 l 394.8 397.92 l 394.8 397.68 l h f 395.28 397.68 m 394.8 397.68 l 402 369.36 l 402 369.12 l 402.24 369.12 l 402.48 369.36 l h f 508.56 369.12 0.24 0.48 re f 402.24 369.6 m 402.24 369.12 l 508.56 369.12 l 508.56 369.6 l h f 394.8 369.36 m 394.8 369.12 l 395.28 369.12 l 395.28 369.36 l h f 394.8 369.36 m 395.28 369.36 l 402.48 397.68 l 402.24 397.92 l 402 397.92 l 402 397.68 l h f 508.56 397.44 0.24 0.48 re f 402.24 397.92 m 402.24 397.44 l 508.56 397.44 l 508.56 397.92 l h f 168.48 397.68 m 168.48 397.92 l 168 397.92 l 168 397.68 l h f 168.48 397.68 m 168 397.68 l 175.2 369.36 l 175.2 369.12 l 175.44 369.12 l 175.68 369.36 l h f 281.76 369.12 0.24 0.48 re f 175.44 369.6 m 175.44 369.12 l 281.76 369.12 l 281.76 369.6 l h f 168 369.36 m 168 369.12 l 168.48 369.12 l 168.48 369.36 l h f 168 369.36 m 168.48 369.36 l 175.68 397.68 l 175.44 397.92 l 175.2 397.92 l 175.2 397.68 l h f 281.76 397.44 0.24 0.48 re f 175.44 397.92 m 175.44 397.44 l 281.76 397.44 l 281.76 397.92 l h f 168.24 397.44 0.24 0.48 re f 139.68 397.44 0.24 0.48 re f 168.24 397.44 m 168.24 397.92 l 139.92 397.92 l 139.92 397.44 l h f 168.24 369.12 0.24 0.48 re f 139.68 369.12 0.24 0.48 re f 168.24 369.12 m 168.24 369.6 l 139.92 369.6 l 139.92 369.12 l h f 515.28 369.36 m 515.28 369.12 l 515.76 369.12 l 515.76 369.36 l h f 508.32 397.68 m 508.32 397.92 l 508.8 397.92 l 508.8 397.68 l h f 515.28 369.36 m 515.76 369.36 l 508.8 397.68 l 508.32 397.68 l h f 508.32 369.36 m 508.32 369.12 l 508.8 369.12 l 508.8 369.36 l h f 515.28 397.68 m 515.28 397.92 l 515.76 397.92 l 515.76 397.68 l h f 508.32 369.36 m 508.8 369.36 l 515.76 397.68 l 515.28 397.68 l h f 536.88 397.44 0.24 0.48 re f 515.28 397.44 0.24 0.48 re f 536.88 397.44 m 536.88 397.92 l 515.52 397.92 l 515.52 397.44 l h f 536.88 369.12 0.24 0.48 re f 515.28 369.12 0.24 0.48 re f 536.88 369.12 m 536.88 369.6 l 515.52 369.6 l 515.52 369.12 l h f BT 410.4 379.2 TD 0.0752 Tc (\(ADR3\)) Tj -226.8 0 TD 0.1152 Tc (\(ADR1\)) Tj 113.28 0 TD (\(ADR2\)) Tj -213.6 156 TD 0.0867 Tc (ADDRESS) Tj 0 -49.68 TD 0.0772 Tc (OPCODE) Tj T* 0.1182 Tc (READ) Tj 0 -56.64 TD 0.0264 Tc (WRITE) Tj ET 1 1 1 rg 72 108.48 468 142.56 re f 0 0 0 rg 168.72 236.88 m 168.72 237.36 l 167.76 237.36 l 167.76 236.88 l h f 168.72 151.92 m 168.72 151.44 l 167.76 151.44 l 167.76 151.92 l h f 167.76 151.92 0.96 84.96 re f 282.24 236.88 m 282.24 237.36 l 281.28 237.36 l 281.28 236.88 l h f 282.24 151.92 m 282.24 151.44 l 281.28 151.44 l 281.28 151.92 l h f 281.28 151.92 0.96 84.96 re f 395.52 236.88 m 395.52 237.36 l 394.56 237.36 l 394.56 236.88 l h f 395.52 151.92 m 395.52 151.44 l 394.56 151.44 l 394.56 151.92 l h f 394.56 151.92 0.96 84.96 re f 509.04 236.88 m 509.04 237.36 l 508.08 237.36 l 508.08 236.88 l h f 509.04 151.92 m 509.04 151.44 l 508.08 151.44 l 508.08 151.92 l h f 508.08 151.92 0.96 84.96 re f 282 194.4 m 282 194.64 l 281.52 194.64 l 281.52 194.4 l h f 282 194.4 m 281.52 194.4 l 288.48 166.08 l 288.48 165.84 l 288.72 165.84 l 288.96 166.08 l h f 395.04 165.84 0.24 0.48 re f 288.72 166.32 m 288.72 165.84 l 395.04 165.84 l 395.04 166.32 l h f 281.52 166.08 m 281.52 165.84 l 282 165.84 l 282 166.08 l h f 281.52 166.08 m 282 166.08 l 288.96 194.4 l 288.72 194.64 l 288.48 194.64 l 288.48 194.4 l h f 395.04 194.16 0.24 0.48 re f 288.72 194.64 m 288.72 194.16 l 395.04 194.16 l 395.04 194.64 l h f 395.28 194.4 m 395.28 194.64 l 394.8 194.64 l 394.8 194.4 l h f 395.28 194.4 m 394.8 194.4 l 402 166.08 l 402 165.84 l 402.24 165.84 l 402.48 166.08 l h f 508.56 165.84 0.24 0.48 re f 402.24 166.32 m 402.24 165.84 l 508.56 165.84 l 508.56 166.32 l h f 394.8 166.08 m 394.8 165.84 l 395.28 165.84 l 395.28 166.08 l h f 394.8 166.08 m 395.28 166.08 l 402.48 194.4 l 402.24 194.64 l 402 194.64 l 402 194.4 l h f 508.56 194.16 0.24 0.48 re f 402.24 194.64 m 402.24 194.16 l 508.56 194.16 l 508.56 194.64 l h f 168.48 194.4 m 168.48 194.64 l 168 194.64 l 168 194.4 l h f 168.48 194.4 m 168 194.4 l 175.2 166.08 l 175.2 165.84 l 175.44 165.84 l 175.68 166.08 l h f 281.76 165.84 0.24 0.48 re f 175.44 166.32 m 175.44 165.84 l 281.76 165.84 l 281.76 166.32 l h f 168 166.08 m 168 165.84 l 168.48 165.84 l 168.48 166.08 l h f 168 166.08 m 168.48 166.08 l 175.68 194.4 l 175.44 194.64 l 175.2 194.64 l 175.2 194.4 l h f 281.76 194.16 0.24 0.48 re f 175.44 194.64 m 175.44 194.16 l 281.76 194.16 l 281.76 194.64 l h f 168.24 194.16 0.24 0.48 re f 139.68 194.16 0.24 0.48 re f 168.24 194.16 m 168.24 194.64 l 139.92 194.64 l 139.92 194.16 l h f 168.24 165.84 0.24 0.48 re f 139.68 165.84 0.24 0.48 re f 168.24 165.84 m 168.24 166.32 l 139.92 166.32 l 139.92 165.84 l h f 515.28 166.08 m 515.28 165.84 l 515.76 165.84 l 515.76 166.08 l h f 508.32 194.4 m 508.32 194.64 l 508.8 194.64 l 508.8 194.4 l h f 515.28 166.08 m 515.76 166.08 l 508.8 194.4 l 508.32 194.4 l h f 508.32 166.08 m 508.32 165.84 l 508.8 165.84 l 508.8 166.08 l h f 515.28 194.4 m 515.28 194.64 l 515.76 194.64 l 515.76 194.4 l h f 508.32 166.08 m 508.8 166.08 l 515.76 194.4 l 515.28 194.4 l h f 536.88 194.16 0.24 0.48 re f 515.28 194.16 0.24 0.48 re f 536.88 194.16 m 536.88 194.64 l 515.52 194.64 l 515.52 194.16 l h f 536.88 165.84 0.24 0.48 re f 515.28 165.84 0.24 0.48 re f 536.88 165.84 m 536.88 166.32 l 515.52 166.32 l 515.52 165.84 l h f BT 410.4 175.92 TD 0.0752 Tc (\(ADR2\)) Tj -113.52 0 TD 0.1152 Tc (\(ADR1\)) Tj ET 282 151.92 m 282 152.16 l 281.52 152.16 l 281.52 151.92 l h f 282 151.92 m 281.52 151.92 l 288.48 123.6 l 288.48 123.36 l 288.72 123.36 l 288.96 123.6 l h f 395.04 123.36 0.24 0.48 re f 288.72 123.84 m 288.72 123.36 l 395.04 123.36 l 395.04 123.84 l h f 281.52 123.6 m 281.52 123.36 l 282 123.36 l 282 123.6 l h f 281.52 123.6 m 282 123.6 l 288.96 151.92 l 288.72 152.16 l 288.48 152.16 l 288.48 151.92 l h f 395.04 151.68 0.24 0.48 re f 288.72 152.16 m 288.72 151.68 l 395.04 151.68 l 395.04 152.16 l h f 395.28 151.92 m 395.28 152.16 l 394.8 152.16 l 394.8 151.92 l h f 395.28 151.92 m 394.8 151.92 l 402 123.6 l 402 123.36 l 402.24 123.36 l 402.48 123.6 l h f 508.56 123.36 0.24 0.48 re f 402.24 123.84 m 402.24 123.36 l 508.56 123.36 l 508.56 123.84 l h f 394.8 123.6 m 394.8 123.36 l 395.28 123.36 l 395.28 123.6 l h f 394.8 123.6 m 395.28 123.6 l 402.48 151.92 l 402.24 152.16 l 402 152.16 l 402 151.92 l h f 508.56 151.68 0.24 0.48 re f 402.24 152.16 m 402.24 151.68 l 508.56 151.68 l 508.56 152.16 l h f 168.48 151.92 m 168.48 152.16 l 168 152.16 l 168 151.92 l h f 168.48 151.92 m 168 151.92 l 175.2 123.6 l 175.2 123.36 l 175.44 123.36 l 175.68 123.6 l h f 281.76 123.36 0.24 0.48 re f 175.44 123.84 m 175.44 123.36 l 281.76 123.36 l 281.76 123.84 l h f 168 123.6 m 168 123.36 l 168.48 123.36 l 168.48 123.6 l h f 168 123.6 m 168.48 123.6 l 175.68 151.92 l 175.44 152.16 l 175.2 152.16 l 175.2 151.92 l h f 281.76 151.68 0.24 0.48 re f 175.44 152.16 m 175.44 151.68 l 281.76 151.68 l 281.76 152.16 l h f 168.24 151.68 0.24 0.48 re f 139.68 151.68 0.24 0.48 re f 168.24 151.68 m 168.24 152.16 l 139.92 152.16 l 139.92 151.68 l h f 168.24 123.36 0.24 0.48 re f 139.68 123.36 0.24 0.48 re f 168.24 123.36 m 168.24 123.84 l 139.92 123.84 l 139.92 123.36 l h f 515.28 123.6 m 515.28 123.36 l 515.76 123.36 l 515.76 123.6 l h f 508.32 151.92 m 508.32 152.16 l 508.8 152.16 l 508.8 151.92 l h f 515.28 123.6 m 515.76 123.6 l 508.8 151.92 l 508.32 151.92 l h f 508.32 123.6 m 508.32 123.36 l 508.8 123.36 l 508.8 123.6 l h f 515.28 151.92 m 515.28 152.16 l 515.76 152.16 l 515.76 151.92 l h f 508.32 123.6 m 508.8 123.6 l 515.76 151.92 l 515.28 151.92 l h f 536.88 151.68 0.24 0.48 re f 515.28 151.68 0.24 0.48 re f 536.88 151.68 m 536.88 152.16 l 515.52 152.16 l 515.52 151.68 l h f 536.88 123.36 0.24 0.48 re f 515.28 123.36 0.24 0.48 re f 536.88 123.36 m 536.88 123.84 l 515.52 123.84 l 515.52 123.36 l h f BT 410.4 133.2 TD 0.0752 Tc (\(ADR3\)) Tj -226.8 0 TD 0.1152 Tc (\(ADR1\)) Tj 113.28 0 TD (\(ADR2\)) Tj -213.6 85.2 TD 0.0772 Tc (OPCODE) Tj 0 -42.48 TD 0.1182 Tc (READ) Tj 0 -42.72 TD 0.0264 Tc (WRITE) Tj ET 282 236.88 m 282 237.12 l 281.52 237.12 l 281.52 236.88 l h f 282 236.88 m 281.52 236.88 l 288.48 208.56 l 288.48 208.32 l 288.72 208.32 l 288.96 208.56 l h f 395.04 208.32 0.24 0.48 re f 288.72 208.8 m 288.72 208.32 l 395.04 208.32 l 395.04 208.8 l h f 281.52 208.56 m 281.52 208.32 l 282 208.32 l 282 208.56 l h f 281.52 208.56 m 282 208.56 l 288.96 236.88 l 288.72 237.12 l 288.48 237.12 l 288.48 236.88 l h f 395.04 236.64 0.24 0.48 re f 288.72 237.12 m 288.72 236.64 l 395.04 236.64 l 395.04 237.12 l h f 395.28 236.88 m 395.28 237.12 l 394.8 237.12 l 394.8 236.88 l h f 395.28 236.88 m 394.8 236.88 l 402 208.56 l 402 208.32 l 402.24 208.32 l 402.48 208.56 l h f 508.56 208.32 0.24 0.48 re f 402.24 208.8 m 402.24 208.32 l 508.56 208.32 l 508.56 208.8 l h f 394.8 208.56 m 394.8 208.32 l 395.28 208.32 l 395.28 208.56 l h f 394.8 208.56 m 395.28 208.56 l 402.48 236.88 l 402.24 237.12 l 402 237.12 l 402 236.88 l h f 508.56 236.64 0.24 0.48 re f 402.24 237.12 m 402.24 236.64 l 508.56 236.64 l 508.56 237.12 l h f 168.48 236.88 m 168.48 237.12 l 168 237.12 l 168 236.88 l h f 168.48 236.88 m 168 236.88 l 175.2 208.56 l 175.2 208.32 l 175.44 208.32 l 175.68 208.56 l h f 281.76 208.32 0.24 0.48 re f 175.44 208.8 m 175.44 208.32 l 281.76 208.32 l 281.76 208.8 l h f 168 208.56 m 168 208.32 l 168.48 208.32 l 168.48 208.56 l h f 168 208.56 m 168.48 208.56 l 175.68 236.88 l 175.44 237.12 l 175.2 237.12 l 175.2 236.88 l h f 281.76 236.64 0.24 0.48 re f 175.44 237.12 m 175.44 236.64 l 281.76 236.64 l 281.76 237.12 l h f 168.24 236.64 0.24 0.48 re f 139.68 236.64 0.24 0.48 re f 168.24 236.64 m 168.24 237.12 l 139.92 237.12 l 139.92 236.64 l h f 168.24 208.32 0.24 0.48 re f 139.68 208.32 0.24 0.48 re f 168.24 208.32 m 168.24 208.8 l 139.92 208.8 l 139.92 208.32 l h f 515.28 208.56 m 515.28 208.32 l 515.76 208.32 l 515.76 208.56 l h f 508.32 236.88 m 508.32 237.12 l 508.8 237.12 l 508.8 236.88 l h f 515.28 208.56 m 515.76 208.56 l 508.8 236.88 l 508.32 236.88 l h f 508.32 208.56 m 508.32 208.32 l 508.8 208.32 l 508.8 208.56 l h f 515.28 236.88 m 515.28 237.12 l 515.76 237.12 l 515.76 236.88 l h f 508.32 208.56 m 508.8 208.56 l 515.76 236.88 l 515.28 236.88 l h f 536.88 236.64 0.24 0.48 re f 515.28 236.64 0.24 0.48 re f 536.88 236.64 m 536.88 237.12 l 515.52 237.12 l 515.52 236.64 l h f 536.88 208.32 0.24 0.48 re f 515.28 208.32 0.24 0.48 re f 536.88 208.32 m 536.88 208.8 l 515.52 208.8 l 515.52 208.32 l h f BT 414.48 218.4 TD 0.1114 Tc (\(PC2\)) Tj -113.28 0 TD 0.1594 Tc (\(PC1\)) Tj ET endstream endobj 39 0 obj 32265 endobj 37 0 obj << /Type /Page /Parent 28 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 38 0 R >> endobj 41 0 obj << /Length 42 0 R >> stream BT 77.76 712.08 TD 0 0 0 rg /F1 12 Tf 0.0067 Tc 3.0026 Tw (The opcode_decoder requires one T2 cycle to decode an opcode. Therefore the result of) Tj -5.76 -14.16 TD 0.048 Tc -0.3065 Tw (opcode_decoder \(the decoded opcode\) and the first immediate operand \(low byte of an immediate) Tj 0 -13.92 TD 0.025 Tc -0.185 Tw (operand or address\) arrive at data_core at the same time:) Tj 5.76 -154.32 TD 0.0338 Tc 1.3742 Tw (For instance, if opcode_decoder generates the control signals for M1 of the data core, it can) Tj -5.76 -14.16 TD 0.0849 Tc -0.4299 Tw (assume that the low byte of an immediate operand or address is available already at the data_core.) Tj 0 -13.92 TD 0.0293 Tc 0.2707 Tw (A read or write operation using short addresses \(or SP offsets\) can therefore start already in M1,) Tj T* 0.0877 Tc -0.2317 Tw (while reads or writes using long addresses must wait until M2.) Tj 0 -29.52 TD /F0 13.92 Tf -0.04 Tc 0 Tw (4.6) Tj 56.64 0 TD 0.0251 Tc (data_core.vhd) Tj -50.88 -18.48 TD /F1 12 Tf 0.0185 Tc 0.7465 Tw (The data_core implements the data paths of the CPU. It consists of two separate parts: \(1\) the) Tj -5.76 -14.16 TD 0.0743 Tc -0.1943 Tw (address calculation and \(2\) the ALU calculation.) Tj 5.76 -19.92 TD 0.0699 Tc 0.6661 Tw (The address calculation consists of two adders and a multiplexer. The inputs of the adders are) Tj -5.76 -13.92 TD 0.1012 Tc -0.4098 Tw (multiplexed from different sources, so that a number of addressing modes are available. The input) Tj 0 -14.16 TD 0.0576 Tc 2.2501 Tw (SA\(4:0\) controls the addressing mode. The signal SP_OP controls, whether the SP shall be) Tj 0 -13.92 TD 0.0577 Tc 0.0794 Tw (updated with the computed address; this is used to implement -\(SP\) and \(SP\)+ addressing modes) Tj T* 0.0333 Tc -0.1773 Tw (and also the MOVE x, SP and ADD x, SP opcodes.) Tj 5.76 -20.16 TD /F0 12 Tf 0 Tc 0 Tw (Examples) Tj 49.92 0 TD /F1 12 Tf (:) Tj 0.96 -19.92 TD -2.64 Tc (\225) Tj 56.64 0 TD /F0 12 Tf 0.012 Tc -0.132 Tw (MOVE LL,\(RR) Tj 80.64 0 TD /F1 12 Tf 0 Tc 0 Tw ( ) Tj 32.88 0 TD 0.03 Tc -0.1671 Tw (SA selects \(0\) +\(0\) + \(RR\) = RR) Tj -170.16 -13.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf 0.06 Tc (CLRB) Tj 56.88 0 TD 0.072 Tc (-\(SP\)) Tj 25.92 0 TD /F1 12 Tf 0 Tc (:) Tj 30.72 0 TD 0.0062 Tc -0.0934 Tw (SA selects \(-1\) + \(0\) + \(SP\) = SP-1. In addition, ) Tj 0 -14.16 TD 0 Tc -0.096 Tw (SP_OP is set to SP_LOAD the that the SP-1 is ) Tj 0 -13.92 TD 0.0171 Tc -0.1771 Tw (loaded into SP. \() Tj 79.92 0 TD /F0 12 Tf 0 Tc 0 Tw (pre) Tj 17.28 0 TD /F1 12 Tf 0.048 Tc -0.048 Tw ( decrement\)) Tj -267.36 -13.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf -0.03 Tc (MOVE) Tj 56.88 0 TD 0.03 Tc (\(SP\)+,RU) Tj 56.64 0 TD /F1 12 Tf -0.0246 Tc -0.0754 Tw (SA selects \(-1\) + \(+1\) + \(SP\) = SP. In contrast to ) Tj 0 -14.16 TD 0.0316 Tc -0.1516 Tw (the previous example, SP_OP is set to SP_INC. ) Tj 0 -13.92 TD 0.041 Tc -0.209 Tw (Therefore the address is SP, but SP is loaded with ) Tj T* -0.048 Tc -0.032 Tw (SP + 1 \() Tj 39.12 0 TD /F0 12 Tf 0 Tc 0 Tw (post) Tj 21.36 0 TD /F1 12 Tf 0.096 Tc -0.096 Tw ( increment\) ) Tj -281.52 -34.08 TD 0.0649 Tc 0.3466 Tw (Appropriate constants for SA are defined in ) Tj 216.96 0 TD /F0 12 Tf -0.01 Tc 0 Tw (cpu_pack.vhd) Tj 71.76 0 TD /F1 12 Tf 0.1076 Tc 0.4067 Tw (. The middle multiplexer \(0 / +1\) is) Tj -294.48 -13.92 TD 0.0492 Tc 0.4708 Tw (used for post increment addressing, but also for the second address \(high byte, n + 1\) of a word) Tj 0 -14.16 TD 0.0141 Tc -0.0941 Tw (access to address n.) Tj ET 1 1 1 rg 72 545.52 468 114.48 re f 444.72 560.88 84.96 42.48 re f 0 0 0 rg 444.72 601.68 86.64 3.12 re f 528.24 559.2 3.12 44.16 re f 443.28 559.2 86.4 3.12 re f 443.28 560.88 3.12 43.92 re f BT 462 576.72 TD /F0 12 Tf 0.0133 Tc 0 Tw (data_core) Tj ET 1 1 1 rg 83.28 603.36 84.96 42.48 re f 0 0 0 rg 83.28 644.16 86.64 3.12 re f 166.8 601.68 3.12 44.16 re f 81.84 601.68 86.4 3.12 re f 81.84 603.36 3.12 43.92 re f BT 104.4 619.2 TD 0.08 Tc (memory) Tj ET 1 1 1 rg 267.6 603.36 99.12 42.48 re f 0 0 0 rg 267.6 644.16 100.8 3.12 re f 365.28 601.68 3.12 44.16 re f 266.16 601.68 100.56 3.12 re f 266.16 603.36 3.12 43.92 re f BT 275.76 619.2 TD -0.0171 Tc (opcode_decoder) Tj -64.8 10.56 TD /F0 9.84 Tf 0.152 Tc (OPC) Tj 176.16 0 TD 0.0528 Tc (CONTROL) Tj ET 256.08 624.48 m 256.08 627.84 l 256.8 627.6 l 265.92 624.96 l 267.6 624.48 l 265.92 624 l 256.8 621.36 l 256.08 621.12 l 256.08 621.84 l 256.56 622.32 l 265.68 624.96 l 265.92 624 l 265.68 624 l 256.56 626.64 l 256.8 627.6 l 257.04 627.12 l 257.04 624.48 l h f 256.08 621.84 m 256.08 624.48 l 257.04 624.48 l 257.04 621.84 l h f 256.56 624.48 m 256.56 627.12 l 265.68 624.48 l 256.56 621.84 l h f* 168 624.24 0.24 0.48 re f 256.08 624.24 0.24 0.48 re f 168.24 624.72 m 168.24 624.24 l 256.08 624.24 l 256.08 624.72 l h f 433.2 575.04 m 433.2 578.4 l 433.92 578.16 l 443.04 575.52 l 444.72 575.04 l 443.04 574.56 l 433.92 571.92 l 433.2 571.68 l 433.2 572.4 l 433.68 572.88 l 442.8 575.52 l 443.04 574.56 l 442.8 574.56 l 433.68 577.2 l 433.92 578.16 l 434.16 577.68 l 434.16 575.04 l h f 433.2 572.4 m 433.2 575.04 l 434.16 575.04 l 434.16 572.4 l h f 433.68 575.04 m 433.68 577.68 l 442.8 575.04 l 433.68 572.4 l h f* 225.36 624.48 m 225.36 624.72 l 224.88 624.72 l 224.88 624.48 l h f 224.88 574.8 0.48 49.68 re f 433.2 574.8 0.24 0.48 re f 225.12 575.28 m 225.12 574.8 l 433.2 574.8 l 433.2 575.28 l h f 433.2 589.2 m 433.2 592.56 l 433.92 592.32 l 443.04 589.68 l 444.72 589.2 l 443.04 588.72 l 433.92 586.08 l 433.2 585.84 l 433.2 586.56 l 433.68 587.04 l 442.8 589.68 l 443.04 588.72 l 442.8 588.72 l 433.68 591.36 l 433.92 592.32 l 434.16 591.84 l 434.16 589.2 l h f 433.2 586.56 m 433.2 589.2 l 434.16 589.2 l 434.16 586.56 l h f 433.68 589.2 m 433.68 591.84 l 442.8 589.2 l 433.68 586.56 l h f* 366.48 624.24 0.24 0.48 re f 366.72 624.24 35.76 0.48 re f 402 588.96 0.48 35.52 re f 433.2 588.96 0.24 0.48 re f 402.24 589.44 m 402.24 588.96 l 433.2 588.96 l 433.2 589.44 l h f endstream endobj 42 0 obj 6256 endobj 40 0 obj << /Type /Page /Parent 28 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 41 0 R >> endobj 44 0 obj << /Length 45 0 R >> stream BT 77.76 322.56 TD 0 0 0 rg /F1 12 Tf 0.0383 Tc 1.1617 Tw (The second part of data_core contains the ALU. The ALU has two inputs, XX and YY. The) Tj -5.76 -14.16 TD 0.0638 Tc -0.2878 Tw (operation of the ALU is controlled by ALU_OP and provides all operations required in C. Appro-) Tj 0 -13.92 TD 0.0133 Tc -0.0933 Tw (priate constants for ) Tj 95.04 0 TD /F0 12 Tf 0.02 Tc 0 Tw (ALU_OP) Tj 47.76 0 TD /F1 12 Tf 0.14 Tc -0.2 Tw ( are defined in ) Tj 72 0 TD /F0 12 Tf -0.01 Tc 0 Tw (cpu_pack.vhd) Tj 71.76 0 TD /F1 12 Tf 0 Tc (.) Tj -280.8 -19.92 TD 0.0192 Tc -0.2845 Tw (The output ZZ of the ALU can be written to registers RR, register LL, or to the memory. A word) Tj -5.76 -14.16 TD 0.1153 Tc -0.262 Tw (write to memory is performed in two M cycles, multiplexing ZZ into its low byte ZL or high byte) Tj 0 -13.92 TD 0.0608 Tc -0.4341 Tw (ZH. The ALU also contains a MIX operation where the \(low\) byte from a memory read in the pre-) Tj T* 0.1117 Tc -0.2317 Tw (vious cycle can be combined with the \(high\) byte of the present cycle.) Tj 5.76 -20.16 TD 0.0442 Tc 0.4358 Tw (The input to the ALU comes from two multiplexers that select the sources of the operand. The) Tj -5.76 -13.92 TD 0.0367 Tc 0.1402 Tw (XX input is one of LL. RR. SP, or PC. The XX input can be ignored through the ALU operation) Tj 0 -13.92 TD /F0 12 Tf 0 Tc 0 Tw (ALU_MOVE_Y) Tj 83.28 0 TD /F1 12 Tf 0.0568 Tc -0.0568 Tw (. Appropriate constants for SX are defined in ) Tj 220.08 0 TD /F0 12 Tf -0.01 Tc 0 Tw (cpu_pack.vhd) Tj 71.76 0 TD /F1 12 Tf 0.0343 Tc 0.0257 Tw (. The YY input can) Tj -375.12 -14.16 TD 0.04 Tc 0.24 Tw (be: SY_0 .. SY_3 \(a fixed value that is independent from the opcode used for PC offsets\), I16 \(a) Tj 0 -13.92 TD 0.0781 Tc 0.365 Tw (collection of immediate operands with different sign-extensions\), QU \(quick: the lower 4 bits of) Tj T* 0.0343 Tc -0.1243 Tw (the opcode\) and MD \(data read from memory or IO\). Appropriate constants for SY are defined in) Tj 0 -14.16 TD /F0 12 Tf -0.01 Tc 0 Tw (cpu_pack.vhd) Tj 71.76 0 TD /F1 12 Tf 0.0727 Tc 0.8873 Tw (. A number of sign extensions are provided through the SX signal, therefore the) Tj -71.76 -13.92 TD 0.0709 Tc 0.2411 Tw (selection of YY has been moved into a separate module ) Tj 275.04 0 TD /F0 12 Tf -0.0092 Tc 0 Tw (select_yy.vhd) Tj 68.16 0 TD /F1 12 Tf 0.036 Tc 0.264 Tw (. The ALU operations are) Tj -343.2 -13.92 TD 0.0873 Tc -0.0873 Tw (contained in ) Tj 61.92 0 TD /F0 12 Tf -0.015 Tc 0 Tw (alu8.vhd) Tj 44.4 0 TD /F1 12 Tf 0 Tc (.) Tj ET 1 1 1 rg 72 338.4 468 369.6 re f 0 0 0 rg 93.36 552 1.44 3.12 re f 121.92 552 1.44 3.12 re f 94.8 555.12 m 94.8 552 l 121.92 552 l 121.92 555.12 l h f BT 0.9827 0 0 1 78.48 550.32 Tm /F0 7.44 Tf 0.0221 Tc (LL) Tj ET 93.36 540.72 1.44 3.12 re f 121.92 540.72 1.44 3.12 re f 94.8 543.84 m 94.8 540.72 l 121.92 540.72 l 121.92 543.84 l h f BT 0.9827 0 0 1 78.48 539.04 Tm 0.0164 Tc (RR) Tj ET 93.36 529.44 1.44 3.12 re f 121.92 529.44 1.44 3.12 re f 94.8 532.56 m 94.8 529.44 l 121.92 529.44 l 121.92 532.56 l h f BT 0.9827 0 0 1 78.48 527.76 Tm 0.0811 Tc (SP) Tj ET 123.6 604.56 m 123.6 582 l 122.4 580.56 l 121.44 583.44 l 137.76 588.96 l 139.92 587.52 l 136.8 587.52 l 136.8 598.8 l 138.72 600.24 l 139.92 599.76 l 139.92 586.56 l 138.72 586.08 l 122.4 580.56 l 120.48 579.84 l 120.48 604.56 l h f 137.76 597.36 m 121.44 603.12 l 120.48 604.56 l 120.48 606.72 l 122.4 606 l 138.72 600.24 l h f BT 0.9827 0 0 1 132.96 620.4 Tm -0.0213 Tc (SA\(4:3\)) Tj ET 93.36 642.24 1.44 3.12 re f 121.92 642.24 1.44 3.12 re f 94.8 645.36 m 94.8 642.24 l 121.92 642.24 l 121.92 645.36 l h f BT 0.9827 0 0 1 78.48 640.56 Tm 0.0535 Tc (I16) Tj ET 93.36 653.52 1.44 3.12 re f 121.92 653.52 1.44 3.12 re f 94.8 656.64 m 94.8 653.52 l 121.92 653.52 l 121.92 656.64 l h f BT 0.9827 0 0 1 78.48 651.84 Tm 0.0875 Tc (-1) Tj ET 93.36 630.96 1.44 3.12 re f 121.92 630.96 1.44 3.12 re f 94.8 634.08 m 94.8 630.96 l 121.92 630.96 l 121.92 634.08 l h f BT 0.9827 0 0 1 78.48 629.28 Tm -0.0139 Tc (I8S) Tj ET 93.36 597.12 1.44 3.12 re f 121.92 597.12 1.44 3.12 re f 94.8 600.24 m 94.8 597.12 l 121.92 597.12 l 121.92 600.24 l h f BT 0.9656 0 0 1 78.48 595.44 Tm /F1 7.44 Tf 0.2567 Tc (0) Tj ET 93.36 585.84 1.44 3.12 re f 121.92 585.84 1.44 3.12 re f 94.8 588.96 m 94.8 585.84 l 121.92 585.84 l 121.92 588.96 l h f BT 0.9827 0 0 1 78.48 584.16 Tm /F0 7.44 Tf 0.0495 Tc (+1) Tj ET 123.6 570.72 m 123.6 525.6 l 122.4 524.16 l 121.44 527.04 l 137.76 532.56 l 139.92 531.12 l 136.8 531.12 l 136.8 564.96 l 138.72 566.4 l 139.92 565.92 l 139.92 530.16 l 138.72 529.68 l 122.4 524.16 l 120.48 523.44 l 120.48 570.72 l h f 137.76 563.52 m 121.44 569.28 l 120.48 570.72 l 120.48 572.88 l 122.4 572.16 l 138.72 566.4 l h f BT 0.9827 0 0 1 129.12 575.28 Tm -0.0649 Tc (SA\(0\)) Tj ET 229.2 593.04 m 228.96 595.2 l 228.96 594.96 l 228.48 597.12 l 228.72 596.64 l 227.52 598.56 l 226.32 600.24 l 226.56 600 l 224.88 601.44 l 225.12 601.2 l 223.44 602.16 l 223.68 602.16 l 221.52 602.88 l 222 602.64 l 219.84 602.88 l 220.08 602.88 l 217.92 602.64 l 218.16 602.88 l 216 602.16 l 216.24 602.16 l 214.56 601.2 l 214.8 601.44 l 213.12 600 l 213.36 600.24 l 211.92 598.56 l 212.16 598.8 l 211.2 596.88 l 211.44 597.12 l 210.96 594.96 l 210.96 595.2 l 210.72 593.04 l 210.72 593.28 l 210.96 590.88 l 210.96 591.12 l 211.44 588.96 l 211.2 589.44 l 212.16 587.52 l 211.92 587.76 l 213.36 586.32 l 213.12 586.56 l 214.8 585.12 l 216.48 583.92 l 216 584.16 l 218.16 583.68 l 217.92 583.68 l 220.08 583.44 l 219.84 583.44 l 222 583.68 l 221.76 583.68 l 223.92 584.16 l 223.2 583.92 l 224.88 585.12 l 226.56 586.56 l 226.32 586.32 l 227.52 587.76 l 227.52 587.52 l 228.72 589.44 l 228.48 588.96 l 228.96 591.12 l 228.96 590.88 l 229.2 593.28 l 232.32 593.04 l 232.08 590.64 l 232.08 590.4 l 231.6 588.24 l 231.36 587.76 l 230.16 585.84 l 229.92 585.84 l 228.72 584.4 l 228.48 584.16 l 226.8 582.72 l 226.8 582.48 l 225.12 581.28 l 224.64 581.04 l 222.48 580.56 l 222.24 580.56 l 220.08 580.32 l 219.84 580.32 l 217.68 580.56 l 217.44 580.56 l 215.28 581.04 l 214.56 581.28 l 212.88 582.48 l 212.88 582.72 l 211.2 584.16 l 209.28 586.08 l 208.32 588 l 208.32 588.24 l 207.84 590.4 l 207.84 590.64 l 207.6 593.04 l 207.6 593.28 l 207.84 595.44 l 207.84 595.68 l 208.32 597.84 l 208.32 598.32 l 209.28 600.24 l 209.52 600.48 l 210.96 602.16 l 211.2 602.4 l 212.88 603.84 l 213.12 603.84 l 214.8 604.8 l 215.04 605.04 l 217.2 605.76 l 217.68 605.76 l 219.84 606 l 220.08 606 l 222.24 605.76 l 222.48 605.76 l 224.64 605.04 l 224.88 604.8 l 226.56 603.84 l 226.8 603.84 l 228.48 602.4 l 228.96 602.16 l 230.16 600.48 l 230.16 600.24 l 231.36 598.32 l 231.6 597.84 l 232.08 595.68 l 232.08 595.44 l 232.32 593.28 l h f 229.2 593.28 m 229.2 593.04 l 232.32 593.28 l 232.32 593.04 l h f 212.88 591.6 1.44 3.12 re f 225.36 591.6 1.44 3.12 re f 214.32 594.72 m 214.32 591.6 l 225.36 591.6 l 225.36 594.72 l h f 221.52 598.8 m 221.52 600.24 l 218.4 600.24 l 218.4 598.8 l h f 221.52 587.52 m 221.52 586.08 l 218.4 586.08 l 218.4 587.52 l h f 218.4 587.52 3.12 11.28 re f 136.8 546.48 1.44 3.12 re f 138.24 546.48 83.28 3.12 re f 218.4 582 m 218.4 583.44 l 221.52 583.44 l 221.52 582 l h f 218.4 548.16 3.12 33.84 re f 473.04 649.68 m 472.56 650.64 l 472.08 651.12 l 470.88 651.12 l 470.4 650.64 l 469.92 649.68 l 470.16 648.96 l 470.4 648.48 l 470.88 648.24 l 472.08 648.24 l 472.56 648.48 l 472.8 648.96 l 473.04 649.68 l h f* 471.36 649.68 m 471.36 655.44 l 472.08 655.2 l 490.08 650.16 l 491.76 649.68 l 490.08 649.2 l 472.08 643.92 l 471.36 643.68 l 471.36 644.4 l 471.84 644.88 l 489.84 650.16 l 490.08 649.2 l 489.84 649.2 l 471.84 654.24 l 472.08 655.2 l 472.32 654.72 l 472.32 649.68 l h f 471.36 644.4 m 471.36 649.68 l 472.32 649.68 l 472.32 644.4 l h f 471.84 649.68 m 471.84 654.72 l 489.84 649.68 l 471.84 644.4 l h f* 272.64 648 1.44 3.12 re f 471.36 648 1.44 3.12 re f 274.08 651.12 m 274.08 648 l 471.36 648 l 471.36 651.12 l h f 229.2 591.6 1.44 3.12 re f 344.88 591.6 1.44 3.12 re f 230.64 594.72 m 230.64 591.6 l 344.88 591.6 l 344.88 594.72 l h f 473.04 598.8 m 472.8 599.52 l 472.56 600 l 472.08 600.24 l 471.36 600.48 l 470.4 600 l 470.16 599.52 l 469.92 598.8 l 470.4 597.84 l 471.36 597.36 l 472.08 597.6 l 472.56 597.84 l 473.04 598.8 l h f* 471.36 598.8 m 471.36 604.8 l 472.08 604.56 l 490.08 599.28 l 491.76 598.8 l 490.08 598.32 l 472.08 593.28 l 471.36 593.04 l 471.36 593.76 l 471.84 594.24 l 489.84 599.28 l 490.08 598.32 l 489.84 598.32 l 471.84 603.6 l 472.08 604.56 l 472.32 604.08 l 472.32 598.8 l h f 471.36 593.76 m 471.36 598.8 l 472.32 598.8 l 472.32 593.76 l h f 471.84 598.8 m 471.84 604.08 l 489.84 598.8 l 471.84 593.76 l h f* 359.76 597.12 1.44 3.12 re f 471.36 597.12 1.44 3.12 re f 361.2 600.24 m 361.2 597.12 l 471.36 597.12 l 471.36 600.24 l h f 324.72 649.68 m 324.72 651.12 l 321.6 651.12 l 321.6 649.68 l h f 321.6 602.88 3.12 46.8 re f 344.88 602.88 1.44 3.12 re f 323.04 606 m 323.04 602.88 l 344.88 602.88 l 344.88 606 l h f BT 0.9827 0 0 1 312.24 566.64 Tm 0.0193 Tc (SP_OP) Tj ET BT 0.9656 0 0 1 334.32 566.64 Tm /F1 7.44 Tf 0.1741 Tc -0.1264 Tw ( \(implies ) Tj ET BT 0.9827 0 0 1 361.68 566.64 Tm /F0 7.44 Tf -0.0215 Tc 0 Tw (WE_SP) Tj ET BT 0.9656 0 0 1 385.68 566.64 Tm /F1 7.44 Tf -0.0442 Tc (\)) Tj ET BT 0.9827 0 0 1 504.96 646.32 Tm /F0 7.44 Tf -0.0194 Tc (MEMADR) Tj ET 382.8 388.56 39.84 3.12 re f 419.52 366 3.12 24.24 re f 381.36 366 39.6 3.12 re f 381.36 367.68 3.12 24 re f BT 0.9827 0 0 1 388.8 375.6 Tm -0.0473 Tc (WE_RR) Tj -129.9341 187.44 TD -0.0219 Tc (SP_NOP) Tj 0 -9.12 TD -0.0127 Tc (SP_INC) Tj T* -0.0559 Tc (SP_LOAD) Tj ET 252.48 576 49.2 0.48 re f 301.2 536.64 0.48 39.6 re f 252.24 536.64 49.2 0.48 re f 252.24 536.88 0.48 39.6 re f 93.36 478.8 1.44 3.12 re f 187.2 478.8 1.44 3.12 re f 94.8 481.92 m 94.8 478.8 l 187.2 478.8 l 187.2 481.92 l h f BT 0.9827 0 0 1 78.48 477.12 Tm 0.0221 Tc (LL) Tj ET 188.88 407.04 m 188.88 361.92 l 187.68 360.48 l 186.72 363.36 l 203.04 369.12 l 205.2 367.68 l 202.08 367.68 l 202.08 401.52 l 204 402.96 l 205.2 402.48 l 205.2 366.72 l 204 366.24 l 187.68 360.48 l 185.76 359.76 l 185.76 407.04 l h f 203.04 400.08 m 186.72 405.6 l 185.76 407.04 l 185.76 409.2 l 187.68 408.48 l 204 402.96 l h f BT 0.9827 0 0 1 504.96 595.44 Tm 0.0811 Tc (SP) Tj ET 202.08 461.76 1.44 3.12 re f 241.68 461.76 1.44 3.12 re f 203.52 464.88 m 203.52 461.76 l 241.68 461.76 l 241.68 464.88 l h f 202.08 382.8 1.44 3.12 re f 241.68 382.8 1.44 3.12 re f 203.52 385.92 m 203.52 382.8 l 241.68 382.8 l 241.68 385.92 l h f 316.32 422.4 1.44 3.12 re f 382.8 422.4 1.44 3.12 re f 317.76 425.52 m 317.76 422.4 l 382.8 422.4 l 382.8 425.52 l h f 382.8 433.68 39.84 3.12 re f 419.52 411.12 3.12 24.24 re f 381.36 411.12 39.6 3.12 re f 381.36 412.8 3.12 24 re f BT 0.9827 0 0 1 389.28 420.72 Tm 0.0038 Tc (WE_LL) Tj ET 473.04 424.08 m 472.56 425.04 l 472.08 425.52 l 470.88 425.52 l 470.4 425.04 l 469.92 424.08 l 470.16 423.36 l 470.4 422.88 l 470.88 422.64 l 472.08 422.64 l 472.56 422.88 l 472.8 423.36 l 473.04 424.08 l h f* 471.36 424.08 m 471.36 429.84 l 472.08 429.6 l 490.08 424.56 l 491.76 424.08 l 490.08 423.6 l 472.08 418.32 l 471.36 418.08 l 471.36 418.8 l 471.84 419.28 l 489.84 424.56 l 490.08 423.6 l 489.84 423.6 l 471.84 428.64 l 472.08 429.6 l 472.32 429.12 l 472.32 424.08 l h f 471.36 418.8 m 471.36 424.08 l 472.32 424.08 l 472.32 418.8 l h f 471.84 424.08 m 471.84 429.12 l 489.84 424.08 l 471.84 418.8 l h f* 419.52 422.4 1.44 3.12 re f 471.36 422.4 1.44 3.12 re f 420.96 425.52 m 420.96 422.4 l 471.36 422.4 l 471.36 425.52 l h f 473.04 378.96 m 472.56 379.92 l 472.08 380.4 l 470.88 380.4 l 470.4 379.92 l 469.92 378.96 l 470.16 378.24 l 470.4 377.76 l 470.88 377.52 l 472.08 377.52 l 472.56 377.76 l 472.8 378.24 l 473.04 378.96 l h f* 471.36 378.96 m 471.36 384.72 l 472.08 384.48 l 490.08 379.44 l 491.76 378.96 l 490.08 378.48 l 472.08 373.2 l 471.36 372.96 l 471.36 373.68 l 471.84 374.16 l 489.84 379.44 l 490.08 378.48 l 489.84 378.48 l 471.84 383.52 l 472.08 384.48 l 472.32 384 l 472.32 378.96 l h f 471.36 373.68 m 471.36 378.96 l 472.32 378.96 l 472.32 373.68 l h f 471.84 378.96 m 471.84 384 l 489.84 378.96 l 471.84 373.68 l h f* 419.52 377.28 1.44 3.12 re f 471.36 377.28 1.44 3.12 re f 420.96 380.4 m 420.96 377.28 l 471.36 377.28 l 471.36 380.4 l h f BT 0.9827 0 0 1 503.76 420.72 Tm 0.0221 Tc (LL) Tj 4.6405 -45.12 TD 0.0164 Tc (RR) Tj -314.0889 58.56 TD 0.001 Tc (SX) Tj 0 -78.96 TD 0.1231 Tc (SY) Tj ET 384.48 486 m 384.48 452.16 l 383.28 450.72 l 382.32 453.6 l 398.64 459.36 l 400.8 457.92 l 397.68 457.92 l 397.68 480.48 l 399.6 481.92 l 400.8 481.44 l 400.8 456.96 l 399.6 456.48 l 383.28 450.72 l 381.36 450 l 381.36 486 l h f 398.64 479.04 m 382.32 484.56 l 381.36 486 l 381.36 488.16 l 383.28 487.44 l 399.6 481.92 l h f 382.8 473.04 1.44 3.12 re f 343.44 473.04 39.36 3.12 re f 343.44 461.76 3.12 12.96 re f 382.8 461.76 1.44 3.12 re f 344.88 464.88 m 344.88 461.76 l 382.8 461.76 l 382.8 464.88 l h f 346.56 463.44 m 346.56 464.88 l 343.44 464.88 l 343.44 463.44 l h f 343.44 377.28 3.12 86.16 re f 382.8 377.28 1.44 3.12 re f 344.88 380.4 m 344.88 377.28 l 382.8 377.28 l 382.8 380.4 l h f 473.04 469.2 m 472.56 470.16 l 472.08 470.64 l 470.88 470.64 l 470.4 470.16 l 469.92 469.2 l 470.16 468.48 l 470.4 468 l 470.88 467.76 l 472.08 467.76 l 472.56 468 l 472.8 468.48 l 473.04 469.2 l h f* 471.36 469.2 m 471.36 474.96 l 472.08 474.72 l 490.08 469.68 l 491.76 469.2 l 490.08 468.72 l 472.08 463.44 l 471.36 463.2 l 471.36 463.92 l 471.84 464.4 l 489.84 469.68 l 490.08 468.72 l 489.84 468.72 l 471.84 473.76 l 472.08 474.72 l 472.32 474.24 l 472.32 469.2 l h f 471.36 463.92 m 471.36 469.2 l 472.32 469.2 l 472.32 463.92 l h f 471.84 469.2 m 471.84 474.24 l 489.84 469.2 l 471.84 463.92 l h f* 435.84 467.52 1.44 3.12 re f 471.36 467.52 1.44 3.12 re f 437.28 470.64 m 437.28 467.52 l 471.36 467.52 l 471.36 470.64 l h f BT 0.9827 0 0 1 504.96 465.84 Tm 0.0528 Tc (MD) Tj -295.5268 5.04 TD 0.0164 Tc (XX) Tj 111.1279 -42.24 TD -0.0257 Tc (ZZ) Tj -111.3721 -39.6 TD 0.0164 Tc (YY) Tj ET 399.12 478.8 39.84 3.12 re f 435.84 456.24 3.12 24.24 re f 397.68 456.24 39.6 3.12 re f 397.68 457.92 3.12 24 re f BT 0.9827 0 0 1 407.04 465.84 Tm 0.016 Tc (WE_M) Tj ET 123.6 672.24 m 123.6 627.12 l 122.4 625.68 l 121.44 628.56 l 137.76 634.08 l 139.92 632.64 l 136.8 632.64 l 136.8 666.48 l 138.72 667.92 l 139.92 667.44 l 139.92 631.68 l 138.72 631.2 l 122.4 625.68 l 120.48 624.96 l 120.48 672.24 l h f 137.76 665.04 m 121.44 670.8 l 120.48 672.24 l 120.48 674.4 l 122.4 673.68 l 138.72 667.92 l h f BT 0.9827 0 0 1 132.96 521.52 Tm -0.0213 Tc (SA\(2:1\)) Tj ET 136.8 591.6 1.44 3.12 re f 209.04 591.6 1.44 3.12 re f 138.24 594.72 m 138.24 591.6 l 209.04 591.6 l 209.04 594.72 l h f 272.64 649.68 m 272.64 651.84 l 272.64 651.36 l 271.92 653.52 l 271.92 653.28 l 270.96 655.2 l 271.2 654.96 l 269.76 656.64 l 270 656.4 l 268.32 657.84 l 268.56 657.6 l 266.88 658.56 l 267.12 658.56 l 264.96 659.28 l 265.44 659.04 l 263.28 659.28 l 263.52 659.28 l 261.36 659.04 l 261.84 659.28 l 259.92 658.56 l 258 657.6 l 258.24 657.84 l 256.56 656.4 l 257.04 656.64 l 255.84 654.96 l 254.64 653.04 l 254.88 653.52 l 254.4 651.36 l 254.4 651.6 l 254.16 649.44 l 254.16 649.68 l 254.4 647.28 l 254.4 647.52 l 254.88 645.36 l 254.64 645.84 l 255.84 643.92 l 255.6 644.16 l 256.8 642.72 l 256.56 642.96 l 258.24 641.52 l 260.16 640.32 l 259.68 640.56 l 261.6 640.08 l 261.36 640.08 l 263.52 639.84 l 263.28 639.84 l 265.44 640.08 l 265.2 640.08 l 267.36 640.56 l 266.64 640.32 l 268.32 641.52 l 270 642.96 l 270 642.72 l 271.44 644.16 l 270.96 643.92 l 271.92 645.84 l 271.92 645.6 l 272.64 647.76 l 272.64 647.28 l 272.64 649.68 l 275.76 649.68 l 275.76 647.28 l 275.52 646.8 l 274.8 644.64 l 274.8 644.4 l 273.6 642 l 272.16 640.56 l 271.92 640.56 l 270.24 639.12 l 270.24 638.88 l 268.56 637.68 l 268.08 637.44 l 265.92 636.96 l 265.68 636.96 l 263.52 636.72 l 263.28 636.72 l 261.12 636.96 l 260.88 636.96 l 258.96 637.44 l 258.48 637.68 l 256.56 638.88 l 256.32 639.12 l 254.64 640.56 l 254.4 640.8 l 253.2 642.24 l 252 644.16 l 251.76 644.64 l 251.28 646.8 l 251.28 647.04 l 251.04 649.44 l 251.04 649.68 l 251.28 651.84 l 251.28 652.08 l 251.76 654.24 l 252 654.72 l 253.2 656.64 l 253.2 656.88 l 254.4 658.56 l 254.64 658.8 l 256.32 660.24 l 256.56 660.48 l 258.48 661.44 l 258.72 661.44 l 260.64 662.16 l 261.12 662.16 l 263.28 662.4 l 263.52 662.4 l 265.68 662.16 l 265.92 662.16 l 268.08 661.44 l 268.32 661.2 l 270 660.24 l 270.24 660.24 l 271.92 658.8 l 272.16 658.56 l 273.6 656.88 l 273.84 656.64 l 274.8 654.72 l 274.8 654.48 l 275.52 652.32 l 275.76 651.84 l 275.76 649.68 l h f 272.64 649.68 m 275.76 649.68 l h f 256.32 648 1.44 3.12 re f 268.8 648 1.44 3.12 re f 257.76 651.12 m 257.76 648 l 268.8 648 l 268.8 651.12 l h f 264.96 655.2 m 264.96 656.64 l 261.84 656.64 l 261.84 655.2 l h f 264.96 643.92 m 264.96 642.48 l 261.84 642.48 l 261.84 643.92 l h f 261.84 643.92 3.12 11.28 re f 93.36 664.8 1.44 3.12 re f 121.92 664.8 1.44 3.12 re f 94.8 667.92 m 94.8 664.8 l 121.92 664.8 l 121.92 667.92 l h f BT 0.9656 0 0 1 78.48 663.12 Tm /F1 7.44 Tf 0.2567 Tc (0) Tj ET 93.36 563.28 1.44 3.12 re f 121.92 563.28 1.44 3.12 re f 94.8 566.4 m 94.8 563.28 l 121.92 563.28 l 121.92 566.4 l h f BT 0.9656 0 0 1 78.48 561.6 Tm (0) Tj ET 136.8 648 1.44 3.12 re f 252.48 648 1.44 3.12 re f 138.24 651.12 m 138.24 648 l 252.48 648 l 252.48 651.12 l h f 346.56 610.08 m 346.56 587.52 l 345.36 586.08 l 344.4 588.96 l 360.72 594.72 l 362.88 593.28 l 359.76 593.28 l 359.76 604.56 l 361.68 606 l 362.88 605.52 l 362.88 592.32 l 361.68 591.84 l 345.36 586.08 l 343.44 585.36 l 343.44 610.08 l h f 360.72 603.12 m 344.4 608.64 l 343.44 610.08 l 343.44 612.24 l 345.36 611.52 l 361.68 606 l h f 261.84 593.28 m 261.84 591.84 l 264.96 591.84 l 264.96 593.28 l h f 261.84 638.4 m 261.84 639.84 l 264.96 639.84 l 264.96 638.4 l h f 261.84 593.28 3.12 45.12 re f BT 0.9827 0 0 1 176.64 552.72 Tm /F0 7.44 Tf -0.0554 Tc (ADR_Z) Tj 0 45.12 TD 0.0018 Tc (ADR_Y) Tj 0 56.4 TD -0.047 Tc (ADR_X) Tj 102.3353 -56.4 TD -0.0434 Tc (ADR_YZ) Tj ET 93.36 467.52 1.44 3.12 re f 187.2 467.52 1.44 3.12 re f 94.8 470.64 m 94.8 467.52 l 187.2 467.52 l 187.2 470.64 l h f BT 0.9827 0 0 1 78.48 465.84 Tm 0.0164 Tc (RR) Tj ET 93.36 456.24 1.44 3.12 re f 187.2 456.24 1.44 3.12 re f 94.8 459.36 m 94.8 456.24 l 187.2 456.24 l 187.2 459.36 l h f BT 0.9827 0 0 1 78.48 454.56 Tm 0.0811 Tc (SP) Tj ET 93.36 366 1.44 3.12 re f 187.2 366 1.44 3.12 re f 94.8 369.12 m 94.8 366 l 187.2 366 l 187.2 369.12 l h f BT 0.9827 0 0 1 78.48 364.32 Tm 0.0164 Tc (RR) Tj 199.0532 -0.72 TD -0.0222 Tc (ALU_OP) Tj ET 188.88 486 m 188.88 440.88 l 187.68 439.44 l 186.72 442.32 l 203.04 448.08 l 205.2 446.64 l 202.08 446.64 l 202.08 480.48 l 204 481.92 l 205.2 481.44 l 205.2 445.68 l 204 445.2 l 187.68 439.44 l 185.76 438.72 l 185.76 486 l h f 203.04 479.04 m 186.72 484.56 l 185.76 486 l 185.76 488.16 l 187.68 487.44 l 204 481.92 l h f 241.68 473.04 77.76 3.12 re f 316.32 371.52 3.12 103.2 re f 240.24 371.52 77.52 3.12 re f 240.24 373.2 3.12 102.96 re f BT 0.9827 0 0 1 250.08 459.6 Tm -0.0535 Tc 0.1483 Tw (XX + YY) Tj 0 -32.64 TD -0.0281 Tc 0.0736 Tw (XX & | ^ ~ YY) Tj 0 -10.8 TD -0.0186 Tc 0.1129 Tw (XX << YY) Tj ET BT 1.2693 0 0 1 250.08 438.48 Tm /F0 5.76 Tf -0.0186 Tc -0.0072 Tw (\(~\) XX < == > ! YY) Tj ET BT 0.9827 0 0 1 250.08 394.32 Tm /F0 7.44 Tf 0.0164 Tc 0.0772 Tw (XX YY) Tj 0 -11.04 TD -0.0439 Tc 0.0775 Tw (XX * / % YY) Tj ET 93.36 444.96 1.44 3.12 re f 187.2 444.96 1.44 3.12 re f 94.8 448.08 m 94.8 444.96 l 187.2 444.96 l 187.2 448.08 l h f BT 0.9827 0 0 1 78.48 443.28 Tm 0.0965 Tc 0 Tw (PC) Tj 174.6295 5.52 TD 0.0039 Tc -0.0322 Tw (\(XX\) - YY) Tj 0 -43.68 TD -0.0186 Tc 0.1129 Tw (XX >> YY) Tj ET 93.36 416.64 1.44 3.12 re f 121.92 416.64 1.44 3.12 re f 94.8 419.76 m 94.8 416.64 l 121.92 416.64 l 121.92 419.76 l h f BT 0.9827 0 0 1 78.48 414.96 Tm 0.1231 Tc 0 Tw (SY) Tj ET 93.36 405.36 1.44 3.12 re f 121.92 405.36 1.44 3.12 re f 94.8 408.48 m 94.8 405.36 l 121.92 405.36 l 121.92 408.48 l h f BT 0.9827 0 0 1 78.48 403.68 Tm 0.0535 Tc (I16) Tj ET 93.36 394.08 1.44 3.12 re f 121.92 394.08 1.44 3.12 re f 94.8 397.2 m 94.8 394.08 l 121.92 394.08 l 121.92 397.2 l h f BT 0.9827 0 0 1 78.48 392.4 Tm 0.0374 Tc (QU) Tj ET 93.36 382.8 1.44 3.12 re f 121.92 382.8 1.44 3.12 re f 94.8 385.92 m 94.8 382.8 l 121.92 382.8 l 121.92 385.92 l h f BT 0.9827 0 0 1 78.48 381.12 Tm 0.0528 Tc (MD) Tj ET 121.92 422.4 39.84 3.12 re f 158.64 377.28 3.12 46.8 re f 120.48 377.28 39.6 3.12 re f 120.48 378.96 3.12 46.56 re f BT 0.9827 0 0 1 132.24 403.2 Tm -0.02 Tc (SIGN) Tj 0.4885 -8.4 TD 0.1507 Tc (IMM) Tj ET 158.64 399.84 1.44 3.12 re f 187.2 399.84 1.44 3.12 re f 160.08 402.96 m 160.08 399.84 l 187.2 399.84 l 187.2 402.96 l h f BT 0.9827 0 0 1 356.88 479.28 Tm 0.0164 Tc (ZH) Tj 0 -25.44 TD 0.1814 Tc (ZL) Tj ET endstream endobj 45 0 obj 21852 endobj 43 0 obj << /Type /Page /Parent 28 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 44 0 R >> endobj 48 0 obj << /Length 49 0 R >> stream BT 72 710.64 TD 0 0 0 rg /F0 13.92 Tf -0.04 Tc 0 Tw (4.7) Tj 56.64 0 TD 0.0366 Tc (select_yy.vhd) Tj -50.88 -18.72 TD /F1 12 Tf 0.08 Tc -0.08 Tw (See ) Tj 20.16 0 TD /F0 12 Tf 0 Tc 0 Tw (data_core.vhd) Tj 72.96 0 TD /F1 12 Tf (.) Tj -98.88 -29.28 TD /F0 13.92 Tf -0.04 Tc (4.8) Tj 56.64 0 TD -0.0054 Tc (alu8.vhd) Tj -50.88 -18.72 TD /F1 12 Tf 0.091 Tc 1.349 Tw (Should actually be alu16.vhd. See) Tj 0 Tc 0 Tw ( ) Tj 174 0 TD /F0 12 Tf 0.0185 Tc (data_core.vhd) Tj 72.96 0 TD /F1 12 Tf 0.0738 Tc 1.3662 Tw (. In order to save slices, the multiplication,) Tj -252.72 -13.92 TD 0.0704 Tc 2.1216 Tw (division, and modulo operations are implemented to do one bit at a time, thus requiring 16) Tj 0 -13.92 TD 0.0971 Tc 0.28 Tw (instructions for a 16 bit multiplication, division, or modulo. The division and modulo results are) Tj 0 -14.16 TD 0.0775 Tc -0.1842 Tw (accessible simultaneously, but C has no operator supporting this directly.) Tj 0 -29.28 TD /F0 13.92 Tf -0.04 Tc 0 Tw (4.9) Tj 56.64 0 TD 0.0333 Tc (opcode_decoder.vhd) Tj -50.88 -18.72 TD /F1 12 Tf 0.08 Tc -0.08 Tw (The ) Tj 21.36 0 TD /F0 12 Tf -0.0171 Tc 0 Tw (opcode_decoder) Tj 82.8 0 TD /F1 12 Tf 0.0677 Tc -0.2544 Tw ( decodes an opcode into the signals required by ) Tj 229.2 0 TD /F0 12 Tf -0.0133 Tc 0 Tw (data_core) Tj 50.64 0 TD /F1 12 Tf 0.016 Tc -0.256 Tw (. It also contains) Tj -389.76 -13.92 TD 0.0904 Tc -0.4264 Tw (a state machine for interrupt handling, which is controlled by an external interrupt signal INT, and) Tj 0 -13.92 TD 0.0492 Tc 0.3451 Tw (by opcodes EI \(enable interrupt\), DI \(disable interrupt\), and HALT \(halt operation until the next) Tj 0 -14.16 TD 0.0824 Tc -0.2569 Tw (interrupt. HALTing the CPU with interrupts disabled will halt the CPU forever.) Tj 54.48 -19.92 TD /F0 12 Tf -0.03 Tc 0 Tw (Note) Tj 24 0 TD /F1 12 Tf 0.06 Tc 0.3 Tw (: The ) Tj 30 0 TD /F0 12 Tf -0.12 Tc 0 Tw (EI) Tj 12.72 0 TD /F1 12 Tf 0.08 Tc 0.4 Tw ( and ) Tj 25.44 0 TD /F0 12 Tf -0.06 Tc 0 Tw (DI) Tj 13.44 0 TD /F1 12 Tf 0.0578 Tc 0.8302 Tw ( opcodes do not directly enable or disable interrupts. Instead a) Tj -105.6 -13.92 TD 0.0584 Tc 1.3096 Tw (counter is incremented resp, decremented. Reset clears the counter, disabling inter-) Tj 0 -14.16 TD 0.1309 Tc -0.3709 Tw (rupts initially. The next ) Tj 114.96 0 TD /F0 12 Tf -0.12 Tc 0 Tw (EI) Tj 12.72 0 TD /F1 12 Tf 0.0908 Tc -0.3608 Tw ( enables interrupts. However, if a number of ) Tj 213.6 0 TD /F0 12 Tf -0.06 Tc 0 Tw (DI) Tj 13.44 0 TD /F1 12 Tf 0.04 Tc -0.28 Tw ( instructions) Tj -354.72 -13.92 TD 0.067 Tc -0.217 Tw (are executed instead, then the according number of ) Tj 247.68 0 TD /F0 12 Tf 0 Tc 0 Tw (EI) Tj 12.48 0 TD /F1 12 Tf 0.0579 Tc -0.1779 Tw ( instructions are required before) Tj -260.16 -13.92 TD 0.0789 Tc 0.5211 Tw (interrupts are enabled. This allows subroutines to disable interrupts independently of) Tj 0 -14.16 TD 0.0867 Tc 0.2013 Tw (other subroutines, which simplifies software development. Executing too many \(> 15) Tj 0 -13.92 TD -0.144 Tc 0.144 Tw (or so\) ) Tj 30.72 0 TD /F0 12 Tf 0.06 Tc 0.06 Tw (DI ) Tj 16.08 0 TD /F1 12 Tf 0.0764 Tc -0.1855 Tw (instructions will cause to counter to overflow, which will crash your system.) Tj -101.28 -29.28 TD /F0 13.92 Tf 0.03 Tc 0 Tw (4.10) Tj 56.64 0 TD 0.0174 Tc (opcode_fetch.vhd) Tj -50.88 -18.72 TD /F1 12 Tf 0.0296 Tc 1.9544 Tw (This is the program counter of the CPU. It is controlled through PC_OP \(generated by the) Tj -5.76 -13.92 TD 0.0316 Tc -0.4516 Tw (opcode_decoder\). The default PC_OP is PC_NEXT, which increments the PC. The other PC_OPs) Tj 0 -14.16 TD 0.16 Tc 0.38 Tw (\(which are defined in ) Tj 108.96 0 TD /F0 12 Tf -0.03 Tc 0 Tw (cpu_pack.vhd) Tj 71.52 0 TD /F1 12 Tf 0.0357 Tc 0.7643 Tw (\) set the PC according to immediate input data \(PC_JMP\),) Tj -180.48 -13.92 TD 0.0253 Tc -0.2653 Tw (values popped from the stack on return from a subroutine \(PC_RETH and PC_RETL\), do nothing) Tj 0 -13.92 TD 0.0499 Tc -0.1779 Tw (when an opcode requires more cycles that its length \(PC_WAIT\), the value of RR \(PC_JPRR\), or) Tj 0 -14.16 TD 0.049 Tc -0.209 Tw (to a fixed address 0x0008 of the interrupt service routine) Tj 0 -36 TD /F0 18 Tf 0.12 Tc 0 Tw (5) Tj 56.64 0 TD 0.0327 Tc -0.2127 Tw (Future Plans) Tj -56.64 -31.2 TD /F0 13.92 Tf -0.04 Tc 0 Tw (5.1) Tj 56.64 0 TD -0.0072 Tc 0.1272 Tw (Wishbone Adaptation) Tj -50.88 -18.72 TD /F1 12 Tf 0.093 Tc 0.612 Tw (This should be fairly straight-forward, but I am wondering if there is any interest in this CPU.) Tj -5.76 -13.92 TD 0.0891 Tc -0.163 Tw (Please feel free to comment if you think a Wishbone Adaptation would be worthwhile.) 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[<37394a77a5eba30d34dd0e762a100ce7><37394a77a5eba30d34dd0e762a100ce7>] >> startxref 140408 %%EOF @ 1.1 log @Initial revision @ text @d3 13 a15 9 BT 176.16 703.92 TD 0 0 0 rg /F0 24 Tf 0.0505 Tc -0.0505 Tw (C16 CPU Documentation) Tj -104.16 -44.88 TD /F0 18 Tf 0.12 Tc 0 Tw (1) Tj 56.64 0 TD 0 Tc -0.06 Tw (History \(why it is as it is\)) Tj -50.88 -23.04 TD /F1 12 Tf 0.0632 Tc 0.2518 Tw (In early 2003, I had finished the design of an STM-1/STM-4 framer. The next step foreard was) Tj -5.76 -13.92 TD 0.0941 Tc -0.2274 Tw (extensive testing, but how? Since I was only using 30% of my FPGA \(a Virtex 100E on an Avnet) Tj 0 -14.16 TD 0.057 Tc -0.267 Tw (board\), I thought a microcontroller on the FPGA would be the easiest solution. The plan was sim-) Tj 0 -13.92 TD 0.0608 Tc 0.0192 Tw (ple enough: download a free CPU core, combine it with the STM framer, and that would be it. A) Tj T* 0.08 Tc -0.2171 Tw (weekend or two should suffice. Well, not exactly.) Tj 5.76 -20.16 TD 0.0896 Tc -0.317 Tw (The first try was an open Z80 core. I chose Z80 since I was programming a lot of Z80 assembler) Tj -5.76 -13.92 TD 0.0585 Tc -0.2985 Tw (back in the 70s \(after the Z80, I fell in love with the 68000\). After downloading the core, I figured) Tj 0 -13.92 TD 0.0668 Tc 0.8265 Tw (that it did not fit into my FPGA. After analyzing the situation, I came to the conclusion, that a) Tj 0 -14.16 TD 0.0949 Tc -0.3649 Tw (8080 would probably be small enough. Since I couldn) Tj -2.64 Tc 0 Tw (\222) Tj 0.08 Tc -0.41 Tw (t a suitable core, I wrote one myself, which) Tj 0 -13.92 TD 0.083 Tc -0.4641 Tw (was finished some weekends later. At some point in time - all instructions were working, but I had) Tj T* 0.0576 Tc 1.1424 Tw (not implemented interrupts yet - I thought it was time to look for a C compiler. I had a small) Tj 0 -14.16 TD 0.0717 Tc 1.3683 Tw (loader that would read intel hex records over a serial interface into the FPGA memory. After) Tj 0 -13.92 TD 0.0708 Tc 0.0845 Tw (searching on the web for some time, I learned that most C compilers were requiring a Z80 rather) Tj T* 0.0849 Tc 0.2351 Tw (than a 8080, and the few 8080 compilers I found had some limitations that I didn) Tj -2.64 Tc 0 Tw (\222) Tj 0.0923 Tc 0.2277 Tw (t like. At least) Tj 0 -14.16 TD 0.0662 Tc -0.2033 Tw (the assemblers I found were ok, so I decided to write my own C compiler.) Tj 5.76 -19.92 TD 0.0765 Tc 2.2935 Tw (A few weekends later, it was already mid 2003, The C compiler for the 8080 was ready.) Tj -5.76 -13.92 TD 0.0686 Tc 0.9284 Tw (Although I exercised some care in generating compact code, even small C programs generated) Tj 0 -14.16 TD 0.081 Tc 0.219 Tw (quite some code, and I had only 8kByte of internal FPGA memory left. I analyzed the generated) Tj 0 -13.92 TD 0.0616 Tc 0.0717 Tw (code, and found that the 8080 was not really made for C. For example, ANDing two 16 bit num-) Tj T* 0.0431 Tc -0.1116 Tw (bers would create a lot of instructions, like:) Tj 28.32 -20.16 TD /F0 12 Tf -0.06 Tc 0 Tw (LD) Tj 56.64 0 TD 0.04 Tc -0.16 Tw (A, C) Tj -56.64 -13.92 TD 0 Tc 0 Tw (AND) Tj 56.64 0 TD -0.12 Tw (A, E) Tj -56.64 -13.92 TD -0.06 Tc 0 Tw (LD) Tj 56.64 0 TD 0 Tc -0.12 Tw (E, A) Tj -56.64 -14.16 TD -0.06 Tc 0 Tw (LD) Tj 56.64 0 TD 0.08 Tc -0.2 Tw (A, B) Tj -56.64 -13.92 TD 0 Tc 0 Tw (AND) Tj 56.64 0 TD 0.04 Tc -0.16 Tw (A, D) Tj -56.64 -13.92 TD -0.06 Tc 0 Tw (LD) Tj 56.64 0 TD 0.04 Tc (D,A) Tj -79.2 -20.16 TD /F1 12 Tf 0.069 Tc -0.369 Tw (Even though \(or actually because\) the 8080 had quite a few registers, the compiler had no choice) Tj -5.76 -13.92 TD 0.0369 Tc -0.4369 Tw (but to move operands back and forth between these registers. Contrary to common wisdom I came) Tj 0 -13.92 TD 0.0486 Tc -0.1153 Tw (to the conclusion that a good CPU does not have as many registers as possible, but instead as few) Tj 0 -14.16 TD 0.0839 Tc -0.2839 Tw (registers as possible. The reasons for this is that \(1\) in FPGAs, internal memory is about as fast as) Tj 0 -13.92 TD 0.1096 Tc 0.2744 Tw (registers, and \(2\) for preemptive multitasking \(which I had in mind from the beginning\), a small) Tj T* 0.0638 Tc 1.8402 Tw (number of registers leads to faster context switches, since all registers need to be saved and) Tj 0 -14.16 TD -0.0533 Tc 0 Tw (restored.) Tj 5.76 -19.92 TD 0.0876 Tc -0.3009 Tw (The next step was then to design my own CPU. Since I was no longer bound by existing compil-) Tj -5.76 -13.92 TD 0.0263 Tc 0.1379 Tw (ers or instruction sets, I could design the CPU in order to suit the compiler, rather than to write a) Tj 0 -14.16 TD 0.0296 Tc 0.9171 Tw (compiler that suits a given CPU. The approach I took was to \(1\) take the 8080 backend of my) Tj 0 -13.92 TD 0.0677 Tc 0.2023 Tw (compiler and to rewrite it towards a hypothetical CPU in such a way that most elementary back-) Tj ET endstream endobj 11 0 obj 4815 endobj 4 0 obj << /Type /Page /Parent 5 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 10 0 R >> endobj 13 0 obj << /Length 14 0 R >> stream BT 72 712.08 TD 0 0 0 rg /F1 12 Tf 0.0644 Tc -0.375 Tw (end operations would need a single 8 bit instruction and \(2\) to design that hypothetical CPU in the) Tj 0 -14.16 TD 0.048 Tc 0 Tw (FPGA.) Tj 5.76 -19.92 TD 0.079 Tc -0.415 Tw (The first decision to make was the number of registers really required. Looking at C expressions,) Tj -5.76 -13.92 TD 0.054 Tc 0.6942 Tw (it turns out that in most nodes of the parsing tree generated by the compiler consists of expres-) Tj 0 -14.16 TD 0.0736 Tc 0.2169 Tw (sions with a left and a right argument. Thus I gave the CPU two registers called LL and RR; LL) Tj 0 -13.92 TD 0.0439 Tc -0.4392 Tw (holds the left argument of a binary operator, RR the right argument, and the result would be stored) Tj T* 0.0972 Tc 0.6934 Tw (in back in RR. For function calls and local variables, a stack pointer, SP, would be required as) Tj 0 -14.16 TD 0.0697 Tc -0.224 Tw (well. This leads to only three registers LL, RR, and SP. and that is enough.) Tj 5.76 -19.92 TD 0.053 Tc -0.069 Tw (The next question is that of addressing modes required. Another common wisdom is that a good) Tj -5.76 -13.92 TD 0.0439 Tc 0.4079 Tw (instruction set is orthogonal, and this turns out to be as wrong as the believe that many registers) Tj 0 -14.16 TD 0.079 Tc 0.116 Tw (are good. In fact, what the compiler really needs is suffucient addressing modes for the leaves of) Tj 0 -13.92 TD 0.0723 Tc 0.1997 Tw (the parse tree \(which are always constants and variables\). Thus the instruction set should be rich) Tj T* 0.066 Tc 2.0571 Tw (in immediated addressing \(e.g. for ++, --, and frequently used binary operators\), SP relative) Tj 0 -14.16 TD 0.0819 Tc 0.0927 Tw (addressing including pre-decrement and post increment for local variables, and absolute address-) Tj 0 -13.92 TD 0.0977 Tc -0.012 Tw (ing for global variables. Orthogonality is not required for these addressing modes, it is suffucient) Tj T* 0.0889 Tc -0.3289 Tw (to have immediate addressing for the RR register only for most binary C operands, while absolute) Tj 0 -14.16 TD 0.0993 Tc -0.1993 Tw (addressing helps also for LL register if a variable is a left operand.) Tj 5.76 -19.92 TD 0.0741 Tc -0.3541 Tw (Another thing to get rid of was a flag register. Considering that in C you can have constructs like) Tj 22.56 -19.92 TD /F0 12 Tf 0.0171 Tc -0.0571 Tw (if \(x > y\)) Tj 113.52 0 TD /F1 12 Tf 0.18 Tc -0.42 Tw (as well as) Tj -113.52 -20.16 TD /F0 12 Tf -0.0343 Tc 0.1543 Tw (z = \(x > y\)) Tj -22.56 -19.92 TD /F1 12 Tf 0.04 Tc 0.5 Tw (it makes more sense to have an opcode for a binary operator ) Tj -2.64 Tc 0 Tw (\221) Tj 0 Tc (>) Tj -2.64 Tc 3.12 Tw (\222 ) Tj -0.01 Tc 0.61 Tw (rather than a compare opcode) Tj -5.76 -13.92 TD 0.0259 Tc 0.4301 Tw (CMP, which sets a flag that needs to be checked later on. The good old 68000 had such a set of) Tj 0 -14.16 TD 0.03 Tc -0.0833 Tw (opcodes \(Scc - set according to condition cc\). Thus the decision was to provide a rich set of com-) Tj 0 -13.92 TD 0.0896 Tc -0.0096 Tw (parison operators and only a limited number of conditional brances \(JMP RRZ and JMP RRNZ -) Tj T* 0.0881 Tc 0.1119 Tw (jump in RR is zero resp. non-zero\) instead of a single compare instruction and a rich set of jump) Tj 0 -14.16 TD 0.0538 Tc -0.1411 Tw (instructions. As a consequence, there is no flag register in our CPU.) Tj 5.76 -19.92 TD 0.0557 Tc 0.7751 Tw (The CPU operastes on 16 bit quantities only; concersion to and from ) Tj 348.24 0 TD /F0 12 Tf -0.06 Tc 0 Tw (char) Tj 23.52 0 TD /F1 12 Tf 0.1108 Tc 0.8492 Tw ( is made when the) Tj -377.52 -13.92 TD 0.0218 Tc 0.2182 Tw (operands are moved into or out of the RR and LL registers \(rather than having the same opcodes) Tj 0 -14.16 TD 0.0733 Tc 0.6467 Tw (for different sizes as with the 68000\), and ) Tj 210.24 0 TD /F0 12 Tf 0 Tc 0 Tw (long) Tj 22.08 0 TD /F1 12 Tf 0.012 Tc 0.738 Tw ( is not supported. The reason for not supporting) Tj -232.32 -13.92 TD /F0 12 Tf -0.06 Tc 0 Tw (long) Tj 22.08 0 TD /F1 12 Tf 0.081 Tc -0.321 Tw ( is essentially FPGA size. A byte operand move into a register is either zero extended or sign) Tj -22.08 -13.92 TD 0.0425 Tc 0.0563 Tw (extended, as dictated by the opcode. In the assembler, we use the notation RU \(R unsigned\) for a) Tj 0 -14.16 TD 0.0523 Tc 0.3289 Tw (byte operand that is zero extended, RS \(R signed\) for a byte operand that is sign extendedm and) Tj 0 -13.92 TD 0.0343 Tc -0.1371 Tw (RR for a word operand. Likewise LU, LS, and LL for the left operand register.) Tj 5.76 -19.92 TD 0.0584 Tc 0.7816 Tw (Most immediate operannd and SP offsets can be short \(8 bit wide\) or long \(16 bit wide\) as to) Tj -5.76 -14.16 TD 0.0457 Tc -0.2057 Tw (reduce the program size.) Tj 0 -36 TD /F0 18 Tf 0.12 Tc 0 Tw (2) Tj 56.64 0 TD -0.03 Tc (Installation) Tj -50.88 -23.04 TD /F1 12 Tf 0.1108 Tc -0.3084 Tw (The CPU comes with an assembler, a C compiler, a simulator, and a few simple utilities for gen-) Tj -5.76 -13.92 TD 0.105 Tc -0.21 Tw (erating vhdl files for the internal memory of the FPGA, communicating with serial ports on a PC,) Tj 0 -13.92 TD 0.0454 Tc 0.2696 Tw (and so on. Everything has been tested on Windows XP, but should also work on other Windows) Tj ET endstream endobj 14 0 obj 5361 endobj 12 0 obj << /Type /Page /Parent 5 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 13 0 R >> endobj 16 0 obj << /Length 17 0 R >> stream BT 72 712.08 TD 0 0 0 rg /F1 12 Tf 0.1037 Tc -0.0472 Tw (versions as well as Linux. I personally prefer Linux, but the fact that my Xilinx tools work under) Tj 0 -14.16 TD 0.0703 Tc -0.1903 Tw (Windows has kind of forced me to do the entire development on Windows.) Tj 0 -29.28 TD /F0 13.92 Tf -0.04 Tc 0 Tw (2.1) Tj 56.64 0 TD 0.0513 Tc (Prerequisites) Tj -50.88 -18.72 TD /F1 12 Tf 0.0576 Tc -0.1605 Tw (For Windows XP, you can use the ) Tj 167.04 0 TD /F0 12 Tf 0.03 Tc 0 Tw (.exe) Tj 19.68 0 TD /F1 12 Tf 0.1371 Tc -0.2571 Tw ( files provided.) Tj -186.72 -19.92 TD 0.06 Tc -0.2446 Tw (For other Windows versions, the tools provided may or may not work without recompilation.) Tj 0 -19.92 TD 0.0655 Tc -0.2026 Tw (For Linux you need to compile the tools.) Tj 0 -20.16 TD 0.1108 Tc -0.3165 Tw (When compilation is required, you should have ) Tj 229.68 0 TD /F0 12 Tf 0.048 Tc 0 Tw (gmake) Tj 33.84 0 TD /F1 12 Tf -0.24 Tc 0.24 Tw (, ) Tj 6 0 TD /F0 12 Tf 0.08 Tc 0 Tw (gcc) Tj 16.56 0 TD /F1 12 Tf -0.24 Tc 0.24 Tw (, ) Tj 5.76 0 TD /F0 12 Tf -0.024 Tc 0 Tw (bison) Tj 27.36 0 TD /F1 12 Tf 0.06 Tc -0.18 Tw (, and ) Tj 26.16 0 TD /F0 12 Tf -0.12 Tc 0 Tw (flex) Tj 18.72 0 TD /F1 12 Tf 0.1067 Tc -0.3467 Tw (. The following sites) Tj -369.84 -13.92 TD 0.042 Tc -0.1106 Tw (are useful for getting these tools for Windows:) Tj 56.64 -40.08 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD 0.0554 Tc (www.mingw.org) Tj 113.52 0 TD 0 Tc (\(gcc\)) Tj -170.16 -13.92 TD -2.64 Tc (\225) Tj 56.64 0 TD -0.0218 Tc (www.gnu.org) Tj 113.52 0 TD 0.1067 Tc -0.1067 Tw (\(gmake, bison, flex\)) Tj -221.04 -34.08 TD 0.12 Tc -0.2 Tw (Even if you don) Tj -2.64 Tc 0 Tw (\222) Tj 0.09 Tc -0.234 Tw (t compile, I would recommend ) Tj 231.36 0 TD /F0 12 Tf 0 Tc 0 Tw (gmake) Tj 34.08 0 TD /F1 12 Tf 0.08 Tc -0.2 Tw ( and ) Tj 23.28 0 TD /F0 12 Tf 0 Tc 0 Tw (gcc) Tj 16.56 0 TD /F1 12 Tf 0.0662 Tc -0.1862 Tw ( at least. Our compiler does little) Tj -311.04 -13.92 TD 0.1003 Tc 0.3797 Tw (type checking, so you should syntax-check your own files with gcc before running the compiler) Tj 0 -13.92 TD 0.0267 Tc 0 Tw (provided.) Tj 0 -29.52 TD /F0 13.92 Tf -0.04 Tc (2.2) Tj 56.64 0 TD 0.0664 Tc -0.1864 Tw (Directory Structure) Tj -50.88 -18.48 TD /F1 12 Tf 0.065 Tc -0.145 Tw (The entire package contains the following directories:) Tj 50.88 -40.08 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf 0.04 Tc (asm) Tj 113.52 0 TD /F1 12 Tf 0.048 Tc -0.168 Tw (source code for the assembler) Tj -170.16 -13.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf 0 Tc (compiler) Tj 113.52 0 TD /F1 12 Tf 0.0384 Tc -0.1344 Tw (source code for the C compiler) Tj -170.16 -14.16 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf 0 Tc (doc) Tj 113.52 0 TD /F1 12 Tf 0.084 Tc -0.204 Tw (contains this document) Tj -170.16 -13.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf 0.08 Tc (memory) Tj 113.52 0 TD /F1 12 Tf 0.016 Tc -0.176 Tw (utility to create ) Tj 74.88 0 TD /F0 12 Tf 0.018 Tc 0 Tw (vhdl/mem_content.vhd) Tj 117.6 0 TD /F1 12 Tf 0.08 Tc -0.56 Tw ( and) Tj 19.92 0 TD /F0 12 Tf 0 Tc -0.36 Tw ( vhdl/) Tj -212.4 -13.92 TD -0.0277 Tc 0 Tw (board_cpu.ucf) Tj 74.16 0 TD /F1 12 Tf 0.1407 Tc -0.2367 Tw ( \(Xilinx and Avnet board specific\)) Tj -244.32 -14.16 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf 0.04 Tc (sim) Tj 113.52 0 TD /F1 12 Tf 0.0288 Tc -0.1488 Tw (source code for the simulator) Tj -170.16 -13.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf -0.06 Tc (vhdl) Tj 113.52 0 TD /F1 12 Tf 0.0424 Tc -0.1624 Tw (vhdl code for the CPU) Tj -226.8 -29.28 TD /F0 13.92 Tf -0.04 Tc 0 Tw (2.3) Tj 56.64 0 TD 0.0196 Tc 0.0524 Tw (Makefiles and Building the Base System) Tj -50.88 -18.72 TD /F1 12 Tf 0.075 Tc -0.235 Tw (There are 3 different targets for the top level Makefile.) Tj 50.88 -40.08 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf -0.04 Tc (loader) Tj 113.52 0 TD /F1 12 Tf 0.0923 Tc -0.2423 Tw (a small program that loads a subsequent memory ) Tj 0 -13.92 TD 0.0825 Tc -0.2196 Tw (image from the serial port of the FPGA.) Tj -170.16 -13.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf 0.03 Tc (test) Tj 113.52 0 TD /F1 12 Tf 0.066 Tc -0.186 Tw (a small monitor program for testing various I/O ) Tj 0 -14.16 TD 0.08 Tc -0.24 Tw (functions of the FPGA) Tj -170.16 -13.92 TD /F0 12 Tf -2.76 Tc 0 Tw (\225) Tj 56.64 0 TD 0 Tc (rtos) Tj 113.52 0 TD /F1 12 Tf 0.0884 Tc -0.2804 Tw (the same monitor as for ) Tj 116.16 0 TD /F0 12 Tf 0.03 Tc 0 Tw (test) Tj 18 0 TD /F1 12 Tf 0.0706 Tc -0.1906 Tw (, but using a preemp-) Tj -134.16 -13.92 TD 0.0852 Tc -0.1652 Tw (tive multitasking operating system) Tj -221.04 -14.16 TD 0.0927 Tc -0.2927 Tw (The anticipated development process is as follows.) Tj 50.88 -19.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD 0.08 Tc -0.24 Tw (Copy the CPU package on your machine) Tj ET endstream endobj 17 0 obj 5059 endobj 15 0 obj << /Type /Page /Parent 5 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 16 0 R >> endobj 19 0 obj << /Length 20 0 R >> stream BT 128.64 712.08 TD 0 0 0 rg /F1 12 Tf -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD 0.1292 Tc -0.3692 Tw (Either install ) Tj 63.84 0 TD /F0 12 Tf 0 Tc 0 Tw (gmake) Tj 34.08 0 TD /F1 12 Tf 0.0545 Tc -0.5825 Tw ( \(recommended\) or else perform the actions in the top ) Tj -97.92 -14.16 TD 0.24 Tc -0.24 Tw (level ) Tj 26.4 0 TD /F0 12 Tf -0.03 Tc 0 Tw (Makefile) Tj 45.36 0 TD /F1 12 Tf 0.135 Tc -0.215 Tw ( manually later on.) Tj -128.4 -13.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD 0.1084 Tc -0.1484 Tw (Build the utilities if required \(see ) Tj 162 0 TD 0.072 Tc -0.168 Tw (2.1 regarding when this is needed\).) Tj -218.64 -13.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD 0.102 Tc -0.27 Tw (If you have a Virtex E evaluation kit from Avnet \() Tj 241.2 0 TD /F0 12 Tf -0.0086 Tc 0 Tw (ADS-XLX-VE-EVL) Tj 102.72 0 TD /F1 12 Tf -0.24 Tc 0.24 Tw (, ) Tj -343.92 -14.16 TD 0.0185 Tc -0.3385 Tw ($150\), then the ) Tj 74.4 0 TD /F0 12 Tf -0.12 Tc 0 Tw (vhdl) Tj 22.56 0 TD /F1 12 Tf 0.0587 Tc -0.495 Tw ( files are ok already. Otherwise, you need to adapt the ) Tj -96.96 -13.92 TD 0.18 Tc -0.24 Tw (top level vhdl file ) Tj 88.08 0 TD /F0 12 Tf -0.02 Tc 0 Tw (vhdl/board_cpu.vhd) Tj 103.68 0 TD /F1 12 Tf 0.1477 Tc -0.2437 Tw ( and the UCF file ) Tj 86.16 0 TD /F0 12 Tf 0 Tc 0 Tw (vhdl/) Tj -277.92 -13.92 TD -0.0277 Tc (board_cpu.ucf) Tj 74.4 0 TD /F1 12 Tf 0.0588 Tc -0.517 Tw ( \(for the Xilinx design flow\) to your actual hardware. Note ) Tj -74.4 -14.16 TD 0.0857 Tc -0.1657 Tw (that the utility ) Tj 70.32 0 TD /F0 12 Tf 0.0514 Tc 0 Tw (memory/makemem) Tj 99.36 0 TD /F1 12 Tf 0.128 Tc -0.308 Tw ( will overwrite the UCF file, so when ) Tj -169.68 -13.92 TD 0.112 Tc -0.24 Tw (you use a different UCF file, then you should use a different name for it, ) Tj 0 -13.92 TD 0.0579 Tc -0.2179 Tw (so that it will not be overwritten,) Tj -56.64 -14.16 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD -0.12 Tc 0.12 Tw (Do ) Tj 17.52 0 TD /F0 12 Tf -0.024 Tc -0.096 Tw (make loader) Tj 63.36 0 TD /F1 12 Tf 0.1029 Tc -0.4329 Tw ( in the top level directory. This compiles ) Tj 195.6 0 TD /F0 12 Tf 0.015 Tc 0 Tw (loader.c) Tj 40.8 0 TD /F1 12 Tf 0 Tc -0.24 Tw ( \(gener-) Tj -317.28 -13.92 TD 0.096 Tc -0.096 Tw (ating ) Tj 27.12 0 TD /F0 12 Tf 0 Tc 0 Tw (loader.asm) Tj 56.16 0 TD /F1 12 Tf 0.1309 Tc -0.1309 Tw (\), assembles ) Tj 61.68 0 TD /F0 12 Tf 0 Tc 0 Tw (loader.asm) Tj 56.4 0 TD /F1 12 Tf 0.1636 Tc -0.3076 Tw ( \(generating a binary file ) Tj -201.36 -13.92 TD /F0 12 Tf -0.012 Tc 0 Tw (loader.bin) Tj 52.32 0 TD /F1 12 Tf 0.192 Tc -0.288 Tw (, an intel hex file ) Tj 84 0 TD /F0 12 Tf -0.036 Tc 0 Tw (loader.ihx) Tj 51.6 0 TD /F1 12 Tf 0.2 Tc -0.296 Tw ( and a list file ) Tj 68.4 0 TD /F0 12 Tf 0.012 Tc 0 Tw (loader.lst) Tj 47.52 0 TD /F1 12 Tf 0 Tc (\), and cre-) Tj -303.84 -14.16 TD (ates ) Tj 21.84 0 TD /F0 12 Tf 0.018 Tc (vhdl/mem_content.vhd) Tj 117.6 0 TD /F1 12 Tf 0.144 Tc -0.204 Tw ( using the utility ) Tj 81.12 0 TD /F0 12 Tf 0.0686 Tc 0 Tw (makemem) Tj 53.28 0 TD /F1 12 Tf 0 Tc (\).) Tj -330.48 -13.92 TD -2.64 Tc (\225) Tj 56.64 0 TD 0.0369 Tc -0.1269 Tw (Compile the VHDL code and download to the FPGA.) Tj -107.52 -34.08 TD 0.0726 Tc 0.1274 Tw (At this point, you should have a working system on a chip. When you connect to the serial port) Tj -5.76 -13.92 TD 0.0273 Tc -0.2407 Tw (of the FPGA \(115,200 kBaud, 8 data bits, no parity, no flow control\) and reset the FPGA, the sys-) Tj 0 -13.92 TD 0.0709 Tc -0.2209 Tw (tem should print the following on the serial output:) Tj 28.32 -20.16 TD /F0 12 Tf -0.048 Tc 0.168 Tw (LOAD >) Tj -22.56 -19.92 TD /F1 12 Tf 0.0911 Tc 0.6571 Tw (This means the system is ready to load the desired application as a series of intel hex records.) Tj -5.76 -13.92 TD 0.0527 Tc -0.4577 Tw (Every intel hex record loaded will be acknowledge by a dot printed on the serial output. Corrupted) Tj 0 -14.16 TD 0.0447 Tc 0.0153 Tw (characters or records are indicated by the message ) Tj 245.28 0 TD /F0 12 Tf -0.03 Tc 0.27 Tw (ERROR: not hex) Tj 88.32 0 TD /F1 12 Tf 0.0923 Tc -0.0123 Tw ( \(invalid character received,) Tj -333.6 -13.92 TD -0.036 Tc -0.012 Tw (check baud rate etc.\) or ) Tj 115.2 0 TD /F0 12 Tf -0.0092 Tc 0.1292 Tw (CHECKSUM ERROR) Tj 116.88 0 TD /F1 12 Tf 0.0646 Tc -0.1246 Tw ( \(rather unlikely to happpen\).) Tj -232.08 -29.28 TD /F0 13.92 Tf -0.04 Tc 0 Tw (2.4) Tj 56.64 0 TD 0.0214 Tc -0.1414 Tw (Building Applications) Tj -50.88 -18.72 TD /F1 12 Tf 0.084 Tc 0.0189 Tw (After the base system containing the loader is working, you can develop your own applications.) Tj -5.76 -13.92 TD 0.0454 Tc -0.114 Tw (Two applications are provided with the CPU: ) Tj 220.8 0 TD /F0 12 Tf 0.03 Tc 0 Tw (test) Tj 18 0 TD /F1 12 Tf 0.16 Tc -0.28 Tw ( and ) Tj 23.28 0 TD /F0 12 Tf 0 Tc 0 Tw (rtos) Tj 20.16 0 TD /F1 12 Tf (.) Tj -276.48 -20.16 TD 0.1029 Tc -0.2229 Tw (To build the application ) Tj 117.84 0 TD /F0 12 Tf 0.03 Tc 0 Tw (test) Tj 18 0 TD /F1 12 Tf 0 Tc -0.12 Tw (, just do) Tj -113.28 -19.92 TD /F0 12 Tf 0.015 Tc 0.105 Tw (make test) Tj -22.56 -19.92 TD /F1 12 Tf 0.048 Tc -0.168 Tw (which creates \(among others\) ) Tj 144.48 0 TD /F0 12 Tf -0.03 Tc 0 Tw (test.ihx) Tj 36.96 0 TD /F1 12 Tf 0.0761 Tc -0.1634 Tw (, which can be loaded into the FPGA via the loader. ) Tj 251.76 0 TD /F0 12 Tf 0.03 Tc 0 Tw (test) Tj 18 0 TD /F1 12 Tf 0.12 Tc -0.12 Tw ( is) Tj -456.96 -14.16 TD 0.1184 Tc 0.9958 Tw (a small monitor that has functions for displaying and modifying memory, setting LEDs on the) Tj 0 -13.92 TD 0.0243 Tc -0.1243 Tw (board, reading the DIP switches on the board, and reading the temperature sensor.) Tj 5.76 -19.92 TD 0.1829 Tc -0.3269 Tw (I was initially using the ) Tj 115.2 0 TD /F0 12 Tf -0.0092 Tc 0 Tw (HyperTerminal) Tj 80.64 0 TD /F1 12 Tf 0.0764 Tc -0.2564 Tw ( program shipped with Windows XP, but copying \(intel) Tj -201.6 -14.16 TD 0.0431 Tc -0.269 Tw (hex\) files to the FPGA was very slow \(even though the baud rate was 115,200\). Therefore I wrote) Tj 0 -13.92 TD 0.0904 Tc 0.081 Tw (the tty.exe program supplied in the package which dumps files much faster on COM1. ) Tj 421.44 0 TD /F0 12 Tf 0 Tc 0 Tw (tty) Tj 13.92 0 TD /F1 12 Tf -0.096 Tc 0.336 Tw ( works) Tj -435.36 -13.92 TD 0.091 Tc -0.091 Tw (from the DOS command line \(program ) Tj 190.56 0 TD /F0 12 Tf 0.08 Tc 0 Tw (cmd) Tj 22.08 0 TD /F1 12 Tf 0.1346 Tc -0.1346 Tw ( in Windows XP\) pretty much like HyperTerminal in) Tj -212.64 -14.16 TD 0.0313 Tc -0.1753 Tw (a window. tty is started as:) Tj 28.32 -19.92 TD /F0 12 Tf 0 Tc 0.12 Tw (tty [filename]) Tj -22.56 -19.92 TD /F1 12 Tf 0.1333 Tc 0.9707 Tw (If no filename is provided, then) Tj 0 Tc 0 Tw ( ) Tj 161.52 0 TD /F0 12 Tf -0.015 Tc (rtos.ihx) Tj 38.88 0 TD /F1 12 Tf 0.1516 Tc 0.8684 Tw ( is assumed by default.) Tj 0 Tc 0 Tw ( ) Tj 118.56 0 TD /F0 12 Tf 0.08 Tc (tty) Tj 14.16 0 TD /F1 12 Tf 0.06 Tc 0.98 Tw ( prints characters received) Tj -338.88 -14.16 TD 0.12 Tc -0.12 Tw (from ) Tj 26.16 0 TD /F0 12 Tf 0.024 Tc 0 Tw (COM1:) Tj 39.36 0 TD /F1 12 Tf 0 Tc -0.16 Tw ( on the ) Tj 35.04 0 TD /F0 12 Tf 0.08 Tc 0 Tw (cmd) Tj 21.84 0 TD /F1 12 Tf 0.1662 Tc -0.4062 Tw ( window in which ) Tj 88.56 0 TD /F0 12 Tf 0 Tc 0 Tw (tty) Tj 13.92 0 TD /F1 12 Tf 0.0229 Tc -0.2895 Tw ( was started and sends characters typed on the key-) Tj ET endstream endobj 20 0 obj 7626 endobj 18 0 obj << /Type /Page /Parent 5 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 19 0 R >> endobj 22 0 obj << /Length 23 0 R >> stream BT 72 712.08 TD 0 0 0 rg /F1 12 Tf -0.0686 Tc -0.0514 Tw (board to ) Tj 42.48 0 TD /F0 12 Tf 0.024 Tc 0 Tw (COM1:) Tj 39.36 0 TD /F1 12 Tf 0.048 Tc -0.108 Tw (. The special character ) Tj 110.88 0 TD /F0 12 Tf -0.06 Tc 0 Tw (^L) Tj 14.88 0 TD /F1 12 Tf 0.08 Tc -0.2 Tw ( causes ) Tj 37.2 0 TD /F0 12 Tf 0 Tc 0 Tw (tty) Tj 13.92 0 TD /F1 12 Tf 0.0554 Tc -0.0954 Tw ( to copy the file ) Tj 81.12 0 TD /F0 12 Tf 0.0133 Tc 0.1067 Tw (filename \() Tj 50.88 0 TD /F1 12 Tf -0.12 Tc 0.12 Tw (or ) Tj 12.96 0 TD /F0 12 Tf -0.015 Tc 0 Tw (rtos.ihx) Tj 39.12 0 TD /F1 12 Tf 0.3 Tc -0.54 Tw ( if no) Tj -442.8 -14.16 TD 0.24 Tc 0 Tw (filename) Tj 42 0 TD /F0 12 Tf 0 Tc 0.12 Tw ( ) Tj 2.88 0 TD /F1 12 Tf 0.0891 Tc -0.1791 Tw (is provided as a command line argument\) to ) Tj 213.84 0 TD /F0 12 Tf 0.024 Tc 0 Tw (COM1:) Tj 39.36 0 TD /F1 12 Tf 0 Tc (.) Tj -298.08 -36 TD /F0 18 Tf 0.12 Tc (3) Tj 56.64 0 TD -0.0189 Tc 0.0789 Tw (Software Description) Tj -56.64 -31.2 TD /F0 13.92 Tf -0.04 Tc 0 Tw (3.1) Tj 56.64 0 TD 0.0512 Tc 0.0688 Tw (C Compiler) Tj -50.88 -18.72 TD /F0 12 Tf -0.0133 Tc 0 Tw (Synopsis:) Tj 79.2 0 TD 0.0207 Tc -0.0507 Tw (cc80 [ -l ] memtop infile [ outfile ]) Tj -79.2 -19.92 TD 0.0267 Tc 0.0933 Tw (Example 1:) Tj 79.2 0 TD 0 Tc 0.06 Tw (cc80 -l 0x2000 loader.c loader.asm) Tj -79.2 -20.16 TD 0.0267 Tc 0.0933 Tw (Example 2:) Tj 79.2 0 TD 0.005 Tc 0.035 Tw (cc80 0x2000 rtos.c rtos.asm) Tj -79.2 -19.92 TD 0.0267 Tc 0 Tw (Function:) Tj 79.2 0 TD /F1 12 Tf 0.1143 Tc 1.3857 Tw (Compile the C source file) Tj 0 Tc 0 Tw ( ) Tj 134.16 0 TD /F0 12 Tf -0.04 Tc (infile) Tj 26.16 0 TD /F1 12 Tf 0.1152 Tc 1.3728 Tw ( and create the assembler file) Tj 0 Tc 0 Tw ( ) Tj 151.92 0 TD /F0 12 Tf -0.0171 Tc (outfile) Tj 32.64 0 TD /F1 12 Tf -0.04 Tc 1.6 Tw (. The -l) Tj -344.88 -13.92 TD 0.0514 Tc -0.0514 Tw (option creates a slightly different startup code intended for a loader, which cop-) Tj 0 -14.16 TD 0.0621 Tc 2.0819 Tw (ies itself to the top of the memory. memtop is the top of the memory \(for) Tj 0 -13.92 TD 0.0662 Tc 0.783 Tw (instance, 0x2000 = 8k for FPGA internal memory, or 0xA000 = 40k when an) Tj T* 0.072 Tc -0.072 Tw (external SRAM is used\).) Tj -79.2 -20.16 TD /F0 12 Tf 0.03 Tc 0 Tw (Limitations:) Tj 79.2 0 TD /F1 12 Tf -0.045 Tc -0.035 Tw (Not too well tested) Tj 0 -19.92 TD -0.0096 Tc -0.0864 Tw (No support for compound \(i.e. ) Tj 149.04 0 TD /F0 12 Tf 0.02 Tc 0 Tw (struct) Tj 30 0 TD /F1 12 Tf 0.0533 Tc -0.0533 Tw (\) function arguments) Tj -179.04 -19.92 TD -0.12 Tc 0.12 Tw (No ) Tj 17.76 0 TD /F0 12 Tf -0.06 Tc 0 Tw (long) Tj 22.08 0 TD /F1 12 Tf -0.03 Tc 0.03 Tw ( data type) Tj -39.84 -20.16 TD 0.0835 Tc -0.2168 Tw (Name should be cc16 \(a left-over from the Z80 compiler\)) Tj -84.96 -29.28 TD /F0 13.92 Tf -0.04 Tc 0 Tw (3.2) Tj 56.64 0 TD 0.0576 Tc (Assembler) Tj -50.88 -18.72 TD /F0 12 Tf -0.0133 Tc (Synopsis:) Tj 79.2 0 TD -0.0115 Tc 0.0515 Tw (assembler infile [ binfile [ listfile[ symfile [ ihxfile ] ] ] ]) Tj -79.2 -19.92 TD 0.03 Tc 0 Tw (Example:) Tj 79.2 0 TD 0.0144 Tc -0.0144 Tw (assembler rtos.asm rtos.bin) Tj -79.2 -19.92 TD 0.0267 Tc 0 Tw (Function:) Tj 79.2 0 TD /F1 12 Tf 0.1366 Tc 0.8418 Tw (Assemble and link the input assembler file and create \(1\) a binary output file) Tj 0 -14.16 TD 0.0978 Tc 0.5879 Tw (\(used by the simulator and by the ) Tj 169.44 0 TD /F0 12 Tf 0.0343 Tc 0 Tw (makemem) Tj 53.28 0 TD /F1 12 Tf 0.1239 Tc 0.699 Tw ( utility\), \(2\) a list file \(useful for) Tj -222.72 -13.92 TD 0.1088 Tc 1.6112 Tw (debugging\), \(3\) a symbol file \(used by the simulator to display source level) Tj 0 -13.92 TD 0.1389 Tc -0.2932 Tw (symbols in a nice way\), and \(4\) an intel hex file \(used by the loader\).) Tj -79.2 -20.16 TD /F0 12 Tf 0 Tc 0 Tw (Limitations) Tj 59.28 0 TD /F1 12 Tf (:) Tj 19.92 0 TD 0.1565 Tc -0.2765 Tw (Can not link several files.) Tj -84.96 -29.28 TD /F0 13.92 Tf -0.04 Tc 0 Tw (3.3) Tj 56.64 0 TD 0.0624 Tc (Simulator) Tj -50.88 -18.72 TD /F0 12 Tf -0.0133 Tc (Synopsis:) Tj 79.2 0 TD -0.0055 Tc 0.0055 Tw (simulate binfile symfile) Tj -79.2 -19.92 TD 0.03 Tc 0 Tw (Example:) Tj 79.2 0 TD 0.015 Tc -0.135 Tw (simulate test.bin test.sym) Tj -79.2 -19.92 TD 0.0267 Tc 0 Tw (Function:) Tj 79.2 0 TD /F1 12 Tf 0.15 Tc -0.15 Tw (Simulate ) Tj 45.84 0 TD /F0 12 Tf -0.0343 Tc 0 Tw (binfile) Tj 32.64 0 TD /F1 12 Tf 0.0884 Tc -0.1684 Tw ( at instruction level.) Tj -157.68 -20.16 TD /F0 12 Tf 0 Tc 0 Tw (Limitations) Tj 59.28 0 TD /F1 12 Tf (:) Tj 19.92 0 TD 0.0768 Tc -0.3168 Tw (Can not simulate interrupts.) Tj -79.2 -19.92 TD /F0 12 Tf 0.0857 Tc 0 Tw (Comment) Tj 50.64 0 TD /F1 12 Tf 0 Tc (:) Tj 28.56 0 TD 0.1075 Tc -0.1293 Tw (The simulator is useful for debugging the compiler and assembler. If something) Tj 0 -13.92 TD 0.0517 Tc 0.7323 Tw (does not work, check if it works in the simulator. If it works in the simulator,) Tj 0 -14.16 TD 0.0494 Tc -0.3044 Tw (then the error is in the hardware \(vhdl\). If it does not work in the simulator, then) Tj 0 -13.92 TD 0.1 Tc -0.292 Tw (the error is in the compiler.) Tj ET endstream endobj 23 0 obj 5301 endobj 21 0 obj << /Type /Page /Parent 5 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 22 0 R >> endobj 25 0 obj << /Length 26 0 R >> stream BT 72 710.64 TD 0 0 0 rg /F0 13.92 Tf -0.04 Tc 0 Tw (3.4) Tj 56.64 0 TD 0.0974 Tc (Makemem) Tj -50.88 -18.72 TD /F0 12 Tf -0.0133 Tc (Synopsis:) Tj 79.2 0 TD 0.0171 Tc 0.1029 Tw (makemem binfile) Tj -79.2 -19.92 TD 0.03 Tc 0 Tw (Example:) Tj 79.2 0 TD 0.0212 Tc 0.0988 Tw (makemem loader.bin) Tj -79.2 -19.92 TD 0.0267 Tc 0 Tw (Function:) Tj 79.2 0 TD /F1 12 Tf 0 Tc (Create ) Tj 34.32 0 TD /F0 12 Tf 0.0052 Tc (../vhdl/mem_content.vhd) Tj 126.96 0 TD /F1 12 Tf 0.18 Tc -0.3 Tw ( from ) Tj 29.28 0 TD /F0 12 Tf -0.0343 Tc 0 Tw (binfile) Tj 32.64 0 TD /F1 12 Tf 0 Tc (.) Tj -302.4 -20.16 TD /F0 12 Tf (Limitations) Tj 59.28 0 TD /F1 12 Tf (:) Tj 19.92 0 TD 0.1239 Tc 0.91 Tw (Output file name should be a command line argument rather than a fixed file) Tj 0 -13.92 TD 0.18 Tc 0 Tw (name) Tj -84.96 -29.28 TD /F0 13.92 Tf -0.04 Tc (3.5) Tj 56.64 0 TD 0 Tc (Tty) Tj -50.88 -18.72 TD /F0 12 Tf -0.0133 Tc (Synopsis:) Tj 79.2 0 TD -0.024 Tc 0.144 Tw (tty ihxfile) Tj -79.2 -19.92 TD 0.03 Tc 0 Tw (Example:) Tj 79.2 0 TD -0.0327 Tc 0.1527 Tw (tty rtos.ihx) Tj -79.2 -20.16 TD 0.0267 Tc 0 Tw (Function:) Tj 79.2 0 TD /F1 12 Tf 0.0893 Tc -0.1579 Tw (Terminal program for Windows. Typing ^L downloads ) Tj 268.08 0 TD /F0 12 Tf -0.0343 Tc 0 Tw (ihxfile) Tj 32.16 0 TD /F1 12 Tf 0 Tc (.) Tj -379.44 -19.92 TD /F0 12 Tf (Limitations) Tj 59.28 0 TD /F1 12 Tf (:) Tj 19.92 0 TD 0.0429 Tc -0.2029 Tw (Baudrate is fixed to 115, 200 Baud) Tj 0 -19.92 TD 0.0267 Tc -0.1139 Tw (Data foirmat fixed to 8 data bits, 1 stop bit, no parity) Tj -84.96 -29.52 TD /F0 13.92 Tf -0.04 Tc 0 Tw (3.6) Tj 56.64 0 TD 0.0368 Tc (Bin2array) Tj -50.88 -18.48 TD /F0 12 Tf -0.0133 Tc (Synopsis:) Tj 79.2 0 TD -0.015 Tc -0.105 Tw (bin2array binfile) Tj -79.2 -20.16 TD 0.03 Tc 0 Tw (Example:) Tj 79.2 0 TD 0.0063 Tc -0.1263 Tw (bin2array loader.bin) Tj -79.2 -19.92 TD 0.0267 Tc 0 Tw (Function:) Tj 79.2 0 TD /F1 12 Tf 0.0761 Tc -0.2132 Tw (Writes a C array respresnting binfile to stdout.) Tj -79.2 -19.92 TD /F0 12 Tf 0.0857 Tc 0 Tw (Comment) Tj 50.64 0 TD /F1 12 Tf 0 Tc (:) Tj 28.56 0 TD 0.0812 Tc 0.2327 Tw (Useful for e.g. providing a loader in an application, so that one application can) Tj 0 -14.16 TD 0.0542 Tc -0.1502 Tw (load another application. See array ) Tj 169.92 0 TD /F0 12 Tf 0.03 Tc 0 Tw (loader[]) Tj 40.56 0 TD /F1 12 Tf 0.08 Tc -0.176 Tw ( in rtos.c for an example.) Tj -295.44 -36 TD /F0 18 Tf 0.12 Tc 0 Tw (4) Tj 56.64 0 TD -0.0095 Tc 0.0695 Tw (Hardware Description) Tj -56.64 -31.2 TD /F0 13.92 Tf -0.04 Tc 0 Tw (4.1) Tj 56.64 0 TD 0.0107 Tc (board_cpu.vhd) Tj -50.88 -18.72 TD /F1 12 Tf 0.1629 Tc -0.3229 Tw (This is the top level design file.) Tj 0 -19.92 TD 0.06 Tc -0.1708 Tw (Adaptations to other boards that the Avnet board should be made in this file.) Tj 0 -20.16 TD 0.1357 Tc -0.2557 Tw (Essentially instantiates ) Tj 112.56 0 TD /F0 12 Tf -0.0133 Tc 0 Tw (cpu16.vhd) Tj 53.04 0 TD /F1 12 Tf 0 Tc (.) Tj -171.36 -29.28 TD /F0 13.92 Tf -0.04 Tc (4.2) Tj 56.64 0 TD 0.0016 Tc (cpu16.vhd) Tj -50.88 -18.72 TD /F1 12 Tf 0.0519 Tc -0.1586 Tw (Breaks down the system on a chip into 3 parts:) Tj 50.88 -19.92 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf -0.0086 Tc (cpu_engine.vhd) Tj 80.4 0 TD /F1 12 Tf -0.24 Tc 0.24 Tw (. ) Tj 33.12 0 TD 0.1171 Tc -0.5704 Tw (This module is the CPU itself, plus 8kByte onchip ) Tj 0 -13.92 TD 0.12 Tc 0 Tw (RAM.) Tj -170.16 -14.16 TD -2.64 Tc (\225) Tj 56.64 0 TD /F0 12 Tf -0.015 Tc (input_output.vhd) Tj 89.76 0 TD /F1 12 Tf 0 Tc ( ) Tj 23.76 0 TD 0.0821 Tc -0.2021 Tw (This module contains the I/O functions of the ) Tj 0 -13.92 TD 0.0324 Tc -0.1224 Tw (Avnet board. You need to rewrite this module ) Tj T* 0.0726 Tc -0.2326 Tw (\(and possibly the applications\) for other boards.) Tj -170.16 -14.16 TD -2.64 Tc 0 Tw (\225) Tj 56.64 0 TD /F0 12 Tf 0 Tc (bin_to_7segment.vhd) Tj 108.96 0 TD /F1 12 Tf 0.0743 Tc -0.1343 Tw (. This module contains a driver that continuously ) Tj 4.56 -13.92 TD 0.0585 Tc -0.3285 Tw (displays the program counter of the CPU. Usefule ) Tj 0 -13.92 TD 0.091 Tc -0.211 Tw (for debugging the system on a chip.) Tj ET endstream endobj 26 0 obj 4302 endobj 24 0 obj << /Type /Page /Parent 5 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 25 0 R >> endobj 29 0 obj << /Length 30 0 R >> stream BT 72 710.64 TD 0 0 0 rg /F0 13.92 Tf -0.04 Tc 0 Tw (4.3) Tj 56.64 0 TD 0.0298 Tc (bin_to_7segment.vhd) Tj -50.88 -18.72 TD /F1 12 Tf 0.098 Tc 1.2353 Tw (This module samples the PC of the CPU at fixed intervals and shows the value on a pair of) Tj -5.76 -13.92 TD 0.0752 Tc -0.1752 Tw (7segment LEDs. This function is specific to the Avnet board providing the LEDs.) Tj 0 -29.28 TD /F0 13.92 Tf -0.04 Tc 0 Tw (4.4) Tj 56.64 0 TD 0 Tc (input_output.vhd) Tj -50.88 -18.72 TD /F1 12 Tf 0.0658 Tc 1.0142 Tw (This module provids a number of I/O functions that can be accessed by the CPU through the) Tj -5.76 -13.92 TD 0.1029 Tc -0.3429 Tw (assembler instructions) Tj 84.96 -20.16 TD /F0 12 Tf 0.06 Tc 0.06 Tw (IN ) Tj 56.88 0 TD 0.0267 Tc -0.1467 Tw (\(port\), RU) Tj 113.28 0 TD /F1 12 Tf 0.08 Tc 0 Tw (and) Tj -170.16 -19.92 TD /F0 12 Tf -0.04 Tc (OUT) Tj 56.88 0 TD 0.06 Tc -0.18 Tw (R, \(port\)) Tj -136.08 -19.92 TD /F1 12 Tf 0.0835 Tc -0.2435 Tw (The ports implemented are:) Tj 152.16 -52.08 TD -0.04 Tc 0.04 Tw (Port Function) Tj 238.56 0 TD -0.12 Tc 0 Tw (IN) Tj 36 0 TD 0 Tc (OUT) Tj -426.48 -24 TD /F0 12 Tf (IN_RX_DATA) Tj 76.56 0 TD /F1 12 Tf 0.0226 Tc -0.219 Tw (: Data to be transmitted on serial output. In polled operation, ) Tj -76.56 -13.92 TD 0.0514 Tc -0.5314 Tw (you need to check ) Tj 88.08 0 TD /F0 12 Tf -0.0133 Tc 0 Tw (IN_STATUS) Tj 66 0 TD /F1 12 Tf 0.0431 Tc -0.4931 Tw ( before sending data. Reading this port resets ) Tj -154.08 -14.16 TD 0.1309 Tc -0.2269 Tw (bits 4 and 0 in ) Tj 71.04 0 TD /F0 12 Tf 0.0133 Tc 0 Tw (IN_STATUS) Tj 66 0 TD /F1 12 Tf 0 Tc (.) Tj 244.56 28.08 TD (0) Tj -381.6 -49.92 TD /F0 12 Tf -0.0133 Tc (IN_STATUS) Tj 66 0 TD /F1 12 Tf 0.0462 Tc -0.1262 Tw (: Status of serial I/O and timer) Tj -66 -14.16 TD 0.016 Tc -0.196 Tw (Bit 7: not used \(0\)) Tj 0 -13.92 TD 0.0758 Tc -0.2067 Tw (Bit 6: 1 iff timer interrupt enabled and timer interrupt has occured) Tj T* 0.0876 Tc -0.2248 Tw (Bit 5:1 iff serial Tx interrupt enabled and serial Tx is ready to accept data) Tj 0 -14.16 TD 0.1163 Tc -0.227 Tw (Bit 4:1 iff serial Rx interrupt enabled and serial Rx has received valid data) Tj 0 -13.92 TD 0.015 Tc -0.195 Tw (Bit 3: :not used \(0\)) Tj T* 0.08 Tc -0.28 Tw (Bit 2:1 iff timer interrupt has occured) Tj 0 -14.16 TD 0.0754 Tc -0.1654 Tw (Bit 1:iff serial Tx is ready to accept data) Tj 0 -13.92 TD 0.1362 Tc -0.2862 Tw (Bit 0:1 iff serial Rx has received valid data) Tj 381.6 112.08 TD 0 Tc 0 Tw (1) Tj -381.6 -134.16 TD /F0 12 Tf -0.0109 Tc (IN_TEMPERAT) Tj 87.36 0 TD /F1 12 Tf 0.036 Tc -0.126 Tw (: current value from temperature sensor \(8 bit 2) Tj -2.64 Tc 0 Tw (\222) Tj 0.09 Tc -0.09 Tw (s comple-) Tj -87.36 -13.92 TD 0.1054 Tc -0.2254 Tw (ment in degrees Celsius\) \(Avnet board specific\)) Tj 381.6 13.92 TD 0 Tc 0 Tw (2) Tj -381.6 -36 TD /F0 12 Tf (IN_DIP_SWITCH) Tj 95.28 0 TD /F1 12 Tf 0.0528 Tc -0.4261 Tw (: current setting of the DIP switch. \(Avnet board specific\)) Tj 286.32 0 TD 0 Tc 0 Tw (3) Tj -381.6 -21.84 TD /F0 12 Tf -0.0086 Tc (IN_CLK_CTR_LOW) Tj 111.84 0 TD /F1 12 Tf 0.0457 Tc -0.1657 Tw (: current value of a 16 bit clock counter \(low byte\)) Tj 269.76 0 TD 0 Tc 0 Tw (4) Tj -381.6 -22.08 TD /F0 12 Tf (IN_CLK_CTR_HIGH) Tj 115.2 0 TD /F1 12 Tf 0.067 Tc -0.2197 Tw (: current value of a 16 bit clock counter \(high byte\)) Tj 266.4 0 TD 0 Tc 0 Tw (5) Tj -381.6 -22.08 TD /F0 12 Tf -0.0109 Tc (OUT_TX_DATA) Tj 88.56 0 TD /F1 12 Tf 0.07 Tc -0.238 Tw (: Data received on serial input. In polled operation, you ) Tj -88.56 -13.92 TD 0 Tc 0 Tw (need to check ) Tj 68.88 0 TD /F0 12 Tf -0.0133 Tc (IN_STATUS) Tj 66 0 TD /F1 12 Tf 0.054 Tc -0.1607 Tw ( before readiing data. Writing this port resets ) Tj -134.88 -13.92 TD 0.1309 Tc -0.2269 Tw (bits 5 and 1 in ) Tj 71.04 0 TD /F0 12 Tf 0.0133 Tc 0 Tw (IN_STATUS) Tj 66 0 TD /F1 12 Tf 0 Tc (.) Tj 287.04 27.84 TD (0) Tj -424.08 -49.92 TD /F0 12 Tf -0.0343 Tc 0.1543 Tw (not used) Tj 424.08 0 TD /F1 12 Tf 0 Tc 0 Tw (1) Tj -424.08 -22.08 TD /F0 12 Tf -0.015 Tc (OUT_LEDS) Tj 63.36 0 TD /F1 12 Tf 0.0261 Tc -0.1461 Tw (: Turns each of the 8 LEDs on or off. 1 turns LED on.\(Avnet ) Tj -63.36 -13.92 TD 0.1029 Tc -0.3429 Tw (board specific\)) Tj 424.08 13.92 TD 0 Tc 0 Tw (2) Tj ET 71.76 100.32 0.48 419.52 re f 453.36 99.84 0.48 420.48 re f 495.84 99.84 0.48 420.48 re f 537.12 100.32 0.48 419.52 re f 71.76 520.32 m 71.76 519.84 l 537.6 519.84 l 537.6 520.32 l h f 72.24 495.6 m 72.24 495.12 l 537.12 495.12 l 537.12 495.6 l h f 72.24 492.96 m 72.24 492.48 l 537.12 492.48 l 537.12 492.96 l h f 71.76 444.24 m 71.76 443.76 l 537.6 443.76 l 537.6 444.24 l h f 71.76 310.32 m 71.76 309.84 l 537.6 309.84 l 537.6 310.32 l h f 71.76 274.32 m 71.76 273.84 l 537.6 273.84 l 537.6 274.32 l h f 71.76 252.24 m 71.76 251.76 l 537.6 251.76 l 537.6 252.24 l h f 71.76 230.16 m 71.76 229.68 l 537.6 229.68 l 537.6 230.16 l h f 71.76 208.32 m 71.76 207.84 l 537.6 207.84 l 537.6 208.32 l h f 71.76 158.16 m 71.76 157.68 l 537.6 157.68 l 537.6 158.16 l h f 71.76 136.32 m 71.76 135.84 l 537.6 135.84 l 537.6 136.32 l h f 71.76 100.32 m 71.76 99.84 l 537.6 99.84 l 537.6 100.32 l h f endstream endobj 30 0 obj 5365 endobj 27 0 obj << /Type /Page /Parent 28 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 29 0 R >> endobj 32 0 obj << /Length 33 0 R >> stream BT 77.76 502.08 TD 0 0 0 rg /F1 12 Tf 0.0554 Tc 0.0779 Tw (The I/O ports are not in the focus of this document, so please refer to the VHDL files regarding) Tj -5.76 -14.16 TD 0.0829 Tc 0.1571 Tw (theit implementation. You may find the baudrate generator interesting due to its unlimited preci-) Tj 0 -13.92 TD 0.064 Tc -0.204 Tw (sion, and the Rx and Tx parts due to their very low size.) Tj 0 -29.28 TD /F0 13.92 Tf -0.04 Tc 0 Tw (4.5) Tj 56.64 0 TD 0.0141 Tc (cpu_engine.vhd) Tj -50.88 -18.72 TD /F1 12 Tf 0.06 Tc -0.14 Tw (This is the CPU itself. The structure of the ) Tj 206.4 0 TD /F0 12 Tf -0.024 Tc 0 Tw (cpu_engine) Tj 58.08 0 TD /F1 12 Tf 0.14 Tc -0.3 Tw ( is as follows:) Tj -264.48 -244.08 TD 0.0512 Tc 0.9088 Tw (The memory signals are also extended to the outside of this module in order to connect to an) Tj -5.76 -13.92 TD 0.0429 Tc -0.1229 Tw (optional external SRAM and to the ) Tj 171.12 0 TD /F0 12 Tf -0.015 Tc 0 Tw (input_output.vhd) Tj 89.76 0 TD /F1 12 Tf 0.1029 Tc -0.3429 Tw ( module.) Tj -255.12 -19.92 TD 0.3105 Tw (The timing is as follows. All signals are clocked on the rising edge of the 40 MHz input clock.) Tj -5.76 -14.16 TD 0.0759 Tc 0.2241 Tw (However, most signals are clocked on every second clock only. This is controlled by the T2 sig-) Tj 0 -13.92 TD 0.0896 Tc -0.0736 Tw (nal. The internal memory is dual-ported, but only to save address and data multiplexers. The first) Tj T* 0.0429 Tc -0.2429 Tw (clock interval \(say T1, or better ) Tj -2.64 Tc 0 Tw (\221) Tj -0.096 Tc -0.144 Tw (not T2) Tj -2.64 Tc 0 Tw (\222) Tj 0.0511 Tc -0.2474 Tw (\) is used for opcode reads, while the second phase \(T2\) is) Tj 0 -14.16 TD 0.0356 Tc -0.1556 Tw (used for all other \(that is, oprand transfers; immediate operands are counted as opcode reads\).) Tj 6 588 TD /F0 12 Tf 0.02 Tc 0 Tw (OUT_INT_MASK) Tj 95.28 0 TD /F1 12 Tf 0.0587 Tc -0.2114 Tw (: The interrupt maks for Rx, Tx and Timer interrupts. 1 ) Tj -95.28 -13.92 TD 0.1 Tc -0.18 Tw (means interrupt is enabled.) Tj 0 -13.92 TD 0 Tc -0.16 Tw (Bit 7..3: not used) Tj 0 -14.16 TD 0.0821 Tc -0.1621 Tw (Bit 2:Enable Timer interrupt \(1 ms interval\)) Tj 0 -13.92 TD 0.0785 Tc -0.2385 Tw (Bit 1: Enable Rx Interrupt \(receiver has received valid data\)) Tj T* 0.0185 Tc -0.1785 Tw (Bit 0: Enable Tx Interrupt \(transmitter ready to accept data\)) Tj 424.08 69.84 TD 0 Tc 0 Tw (3) Tj -424.08 -91.92 TD /F0 12 Tf -0.024 Tc (OUT_RESET_TIMER) Tj 117.84 0 TD /F1 12 Tf 0.0857 Tc -0.1457 Tw (: Writing clears Timer interrupt) Tj 306.24 0 TD 0 Tc 0 Tw (4) Tj -424.08 -22.08 TD /F0 12 Tf -0.0141 Tc (OUT_START_CLK_CTR) Tj 135.36 0 TD /F1 12 Tf -0.0065 Tc -0.1135 Tw (: Start a 16 bit counter clocked at a rate of 20 ) Tj -135.36 -13.92 TD 0.1111 Tc -0.2611 Tw (MHz. Useful for measuring short intervals with high precision.) Tj 424.08 13.92 TD 0 Tc 0 Tw (5) Tj -424.08 -36 TD /F0 12 Tf -0.0075 Tc (OUT_STOP_CLK_CTR) Tj 126.72 0 TD /F1 12 Tf -0.024 Tc -0.072 Tw (: Stop the 16 bit counter) Tj 25.2 174 TD -0.04 Tc 0.04 Tw (Port Function) Tj 238.56 0 TD -0.12 Tc 0 Tw (IN) Tj 36 0 TD 0 Tc (OUT) Tj ET 71.76 522.24 0.48 197.52 re f 453.36 521.76 0.48 198.48 re f 495.84 521.76 0.48 198.48 re f 537.12 522.24 0.48 197.52 re f 71.76 720.24 m 71.76 719.76 l 537.6 719.76 l 537.6 720.24 l h f 72.24 695.52 m 72.24 695.04 l 537.12 695.04 l 537.12 695.52 l h f 72.24 693.12 m 72.24 692.64 l 537.12 692.64 l 537.12 693.12 l h f 71.76 602.16 m 71.76 601.68 l 537.6 601.68 l 537.6 602.16 l h f 71.76 580.32 m 71.76 579.84 l 537.6 579.84 l 537.6 580.32 l h f 71.76 544.32 m 71.76 543.84 l 537.6 543.84 l 537.6 544.32 l h f 71.76 522.24 m 71.76 521.76 l 537.6 521.76 l 537.6 522.24 l h f 1 1 1 rg 72 217.92 468 184.08 re f 444.72 239.04 84.96 42.48 re f 0 0 0 rg 444.72 279.84 86.64 3.12 re f 528.24 237.36 3.12 44.16 re f 443.28 237.36 86.4 3.12 re f 443.28 239.04 3.12 43.92 re f BT 462 254.88 TD /F0 12 Tf 0.0133 Tc (data_core) Tj ET 1 1 1 rg 260.4 239.04 85.2 42.48 re f 0 0 0 rg 260.4 279.84 86.88 3.12 re f 344.16 237.36 3.12 44.16 re f 258.96 237.36 86.64 3.12 re f 258.96 239.04 3.12 43.92 re f BT 281.76 254.88 TD 0.08 Tc (memory) Tj ET 1 1 1 rg 76.32 239.04 84.96 42.48 re f 0 0 0 rg 76.32 279.84 86.64 3.12 re f 159.84 237.36 3.12 44.16 re f 74.88 237.36 86.4 3.12 re f 74.88 239.04 3.12 43.92 re f BT 85.2 254.88 TD 0.01 Tc (opcode_fetch) Tj ET 1 1 1 rg 253.44 338.16 99.12 42.48 re f 0 0 0 rg 253.44 378.96 100.8 3.12 re f 351.12 336.48 3.12 44.16 re f 252 336.48 100.56 3.12 re f 252 338.16 3.12 43.92 re f BT 261.6 354.24 TD -0.0171 Tc (opcode_decoder) Tj ET 248.88 260.16 m 248.88 263.52 l 249.6 263.28 l 258.96 260.64 l 260.64 260.16 l 258.96 259.68 l 249.6 257.04 l 248.88 256.8 l 248.88 257.52 l 249.36 258 l 258.72 260.64 l 258.96 259.68 l 258.72 259.68 l 249.36 262.32 l 249.6 263.28 l 249.84 262.8 l 249.84 260.16 l h f 248.88 257.52 m 248.88 260.16 l 249.84 260.16 l 249.84 257.52 l h f 249.36 260.16 m 249.36 262.8 l 258.72 260.16 l 249.36 257.52 l h f* 161.04 259.92 0.24 0.48 re f 248.88 259.92 0.24 0.48 re f 161.28 260.4 m 161.28 259.92 l 248.88 259.92 l 248.88 260.4 l h f 357.12 274.32 m 357.12 270.96 l 356.4 271.2 l 347.04 273.84 l 345.36 274.32 l 347.04 274.8 l 356.4 277.68 l 357.12 277.92 l 357.12 277.2 l 356.64 276.72 l 347.28 273.84 l 347.04 274.8 l 347.28 274.8 l 356.64 272.16 l 356.4 271.2 l 356.16 271.68 l 356.16 274.32 l h f 357.12 277.2 m 357.12 274.32 l 356.16 274.32 l 356.16 277.2 l h f 356.64 274.32 m 356.64 271.68 l 347.28 274.32 l 356.64 277.2 l h f* 356.88 274.08 0.24 0.48 re f 444.72 274.08 0.24 0.48 re f 357.12 274.56 m 357.12 274.08 l 444.72 274.08 l 444.72 274.56 l h f 274.56 326.64 m 271.2 326.64 l 271.44 327.36 l 274.08 336.72 l 274.56 338.4 l 275.04 336.72 l 277.68 327.36 l 277.92 326.64 l 277.2 326.64 l 276.72 327.12 l 274.08 336.48 l 275.04 336.72 l 275.04 336.48 l 272.4 327.12 l 271.44 327.36 l 271.92 327.6 l 274.56 327.6 l h f 277.2 326.64 m 274.56 326.64 l 274.56 327.6 l 277.2 327.6 l h f 274.56 327.12 m 271.92 327.12 l 274.56 336.48 l 277.2 327.12 l h f* 274.32 281.52 m 274.32 281.28 l 274.8 281.28 l 274.8 281.52 l h f 274.32 326.64 m 274.32 326.88 l 274.8 326.88 l 274.8 326.64 l h f 274.32 281.52 0.48 45.12 re f 357.12 260.16 m 357.12 256.8 l 356.4 257.04 l 347.04 259.68 l 345.36 260.16 l 347.04 260.64 l 356.4 263.28 l 357.12 263.52 l 357.12 262.8 l 356.64 262.32 l 347.28 259.68 l 347.04 260.64 l 347.28 260.64 l 356.64 258 l 356.4 257.04 l 356.16 257.52 l 356.16 260.16 l h f 357.12 262.8 m 357.12 260.16 l 356.16 260.16 l 356.16 262.8 l h f 356.64 260.16 m 356.64 257.52 l 347.28 260.16 l 356.64 262.8 l h f* 356.88 259.92 0.24 0.48 re f 444.72 259.92 0.24 0.48 re f 357.12 260.4 m 357.12 259.92 l 444.72 259.92 l 444.72 260.4 l h f BT 175.44 262.32 TD /F0 9.84 Tf 0.1056 Tc (PC) Tj 106.56 45.84 TD 0.152 Tc (OPC) Tj ET 487.2 293.04 m 490.56 293.04 l 490.32 292.32 l 487.68 283.2 l 487.2 281.52 l 486.72 283.2 l 484.08 292.32 l 483.84 293.04 l 484.56 293.04 l 485.04 292.56 l 487.68 283.44 l 486.72 283.2 l 486.72 283.44 l 489.36 292.56 l 490.32 292.32 l 489.84 292.08 l 487.2 292.08 l h f 484.56 293.04 m 487.2 293.04 l 487.2 292.08 l 484.56 292.08 l h f 487.2 292.56 m 489.84 292.56 l 487.2 283.44 l 484.56 292.56 l h f* 352.32 359.28 0.24 0.48 re f 356.4 359.28 0.24 0.48 re f 352.56 359.76 m 352.56 359.28 l 356.4 359.28 l 356.4 359.76 l h f 362.4 359.28 0.24 0.48 re f* 369.84 359.28 0.24 0.48 re f* 362.64 359.76 m 362.64 359.28 l 369.84 359.28 l 369.84 359.76 l h f* 375.84 359.28 0.24 0.48 re f* 383.28 359.28 0.24 0.48 re f* 376.08 359.76 m 376.08 359.28 l 383.28 359.28 l 383.28 359.76 l h f* 389.28 359.28 0.24 0.48 re f* 396.72 359.28 0.24 0.48 re f* 389.52 359.76 m 389.52 359.28 l 396.72 359.28 l 396.72 359.76 l h f* 402.72 359.28 0.24 0.48 re f* 410.16 359.28 0.24 0.48 re f* 402.96 359.76 m 402.96 359.28 l 410.16 359.28 l 410.16 359.76 l h f* 416.16 359.28 0.24 0.48 re f* 423.6 359.28 0.24 0.48 re f* 416.4 359.76 m 416.4 359.28 l 423.6 359.28 l 423.6 359.76 l h f* 429.6 359.28 0.24 0.48 re f* 437.04 359.28 0.24 0.48 re f* 429.84 359.76 m 429.84 359.28 l 437.04 359.28 l 437.04 359.76 l h f* 443.04 359.28 0.24 0.48 re f* 450.48 359.28 0.24 0.48 re f* 443.28 359.76 m 443.28 359.28 l 450.48 359.28 l 450.48 359.76 l h f* 456.48 359.28 0.24 0.48 re f* 463.92 359.28 0.24 0.48 re f* 456.72 359.76 m 456.72 359.28 l 463.92 359.28 l 463.92 359.76 l h f* 469.92 359.28 0.24 0.48 re f* 477.36 359.28 0.24 0.48 re f* 470.16 359.76 m 470.16 359.28 l 477.36 359.28 l 477.36 359.76 l h f* 483.36 359.28 0.24 0.48 re f 483.6 359.28 3.84 0.48 re f 487.44 355.68 m 487.44 355.44 l 486.96 355.44 l 486.96 355.68 l h f 486.96 355.68 0.48 3.84 re f 487.44 349.68 m 487.44 349.92 l 486.96 349.92 l 486.96 349.68 l h f* 487.44 342.48 m 487.44 342.24 l 486.96 342.24 l 486.96 342.48 l h f* 486.96 342.48 0.48 7.2 re f* 487.44 336.48 m 487.44 336.72 l 486.96 336.72 l 486.96 336.48 l h f* 487.44 329.28 m 487.44 329.04 l 486.96 329.04 l 486.96 329.28 l h f* 486.96 329.28 0.48 7.2 re f* 487.44 323.28 m 487.44 323.52 l 486.96 323.52 l 486.96 323.28 l h f* 487.44 316.08 m 487.44 315.84 l 486.96 315.84 l 486.96 316.08 l h f* 486.96 316.08 0.48 7.2 re f* 487.44 310.08 m 487.44 310.32 l 486.96 310.32 l 486.96 310.08 l h f* 487.44 302.88 m 487.44 302.64 l 486.96 302.64 l 486.96 302.88 l h f* 486.96 302.88 0.48 7.2 re f* 487.44 296.88 m 487.44 297.12 l 486.96 297.12 l 486.96 296.88 l h f 487.44 293.04 m 487.44 292.8 l 486.96 292.8 l 486.96 293.04 l h f 486.96 293.04 0.48 3.84 re f 118.8 293.04 m 122.16 293.04 l 121.92 292.32 l 119.28 283.2 l 118.8 281.52 l 118.32 283.2 l 115.68 292.32 l 115.44 293.04 l 116.16 293.04 l 116.64 292.56 l 119.28 283.44 l 118.32 283.2 l 118.32 283.44 l 120.96 292.56 l 121.92 292.32 l 121.44 292.08 l 118.8 292.08 l h f 116.16 293.04 m 118.8 293.04 l 118.8 292.08 l 116.16 292.08 l h f 118.8 292.56 m 121.44 292.56 l 118.8 283.44 l 116.16 292.56 l h f* 253.44 352.08 0.24 0.48 re f 249.36 352.08 0.24 0.48 re f 253.44 352.08 m 253.44 352.56 l 249.6 352.56 l 249.6 352.08 l h f 243.36 352.08 0.24 0.48 re f* 235.92 352.08 0.24 0.48 re f* 243.36 352.08 m 243.36 352.56 l 236.16 352.56 l 236.16 352.08 l h f* 229.92 352.08 0.24 0.48 re f* 222.48 352.08 0.24 0.48 re f* 229.92 352.08 m 229.92 352.56 l 222.72 352.56 l 222.72 352.08 l h f* 216.48 352.08 0.24 0.48 re f* 209.04 352.08 0.24 0.48 re f* 216.48 352.08 m 216.48 352.56 l 209.28 352.56 l 209.28 352.08 l h f* 203.04 352.08 0.24 0.48 re f* 195.6 352.08 0.24 0.48 re f* 203.04 352.08 m 203.04 352.56 l 195.84 352.56 l 195.84 352.08 l h f* 189.6 352.08 0.24 0.48 re f* 182.16 352.08 0.24 0.48 re f* 189.6 352.08 m 189.6 352.56 l 182.4 352.56 l 182.4 352.08 l h f* 176.16 352.08 0.24 0.48 re f* 168.72 352.08 0.24 0.48 re f* 176.16 352.08 m 176.16 352.56 l 168.96 352.56 l 168.96 352.08 l h f* 162.72 352.08 0.24 0.48 re f* 155.28 352.08 0.24 0.48 re f* 162.72 352.08 m 162.72 352.56 l 155.52 352.56 l 155.52 352.08 l h f* 149.28 352.08 0.24 0.48 re f* 141.84 352.08 0.24 0.48 re f* 149.28 352.08 m 149.28 352.56 l 142.08 352.56 l 142.08 352.08 l h f* 135.84 352.08 0.24 0.48 re f* 128.4 352.08 0.24 0.48 re f* 135.84 352.08 m 135.84 352.56 l 128.64 352.56 l 128.64 352.08 l h f* 122.4 352.08 0.24 0.48 re f 118.56 352.08 3.84 0.48 re f 119.04 348.72 m 119.04 348.48 l 118.56 348.48 l 118.56 348.72 l h f 118.56 348.72 0.48 3.6 re f 119.04 341.76 m 119.04 342 l 118.56 342 l 118.56 341.76 l h f* 119.04 333.6 m 119.04 333.36 l 118.56 333.36 l 118.56 333.6 l h f* 118.56 333.6 0.48 8.16 re f* 119.04 326.64 m 119.04 326.88 l 118.56 326.88 l 118.56 326.64 l h f* 119.04 318.72 m 119.04 318.48 l 118.56 318.48 l 118.56 318.72 l h f* 118.56 318.72 0.48 7.92 re f* 119.04 311.76 m 119.04 312 l 118.56 312 l 118.56 311.76 l h f* 119.04 303.84 m 119.04 303.6 l 118.56 303.6 l 118.56 303.84 l h f* 118.56 303.84 0.48 7.92 re f* 119.04 296.88 m 119.04 297.12 l 118.56 297.12 l 118.56 296.88 l h f 119.04 293.04 m 119.04 292.8 l 118.56 292.8 l 118.56 293.04 l h f 118.56 293.04 0.48 3.84 re f 324.24 293.04 m 327.6 293.04 l 327.36 292.32 l 324.72 283.2 l 324.24 281.52 l 323.76 283.2 l 321.12 292.32 l 320.88 293.04 l 321.6 293.04 l 322.08 292.56 l 324.72 283.44 l 323.76 283.2 l 323.76 283.44 l 326.4 292.56 l 327.36 292.32 l 326.88 292.08 l 324.24 292.08 l h f 321.6 293.04 m 324.24 293.04 l 324.24 292.08 l 321.6 292.08 l h f 324.24 292.56 m 326.88 292.56 l 324.24 283.44 l 321.6 292.56 l h f* 324.48 338.16 m 324.48 338.4 l 324 338.4 l 324 338.16 l h f 324.48 334.56 m 324.48 334.32 l 324 334.32 l 324 334.56 l h f 324 334.56 0.48 3.6 re f 324.48 327.36 m 324.48 327.6 l 324 327.6 l 324 327.36 l h f* 324.48 319.2 m 324.48 318.96 l 324 318.96 l 324 319.2 l h f* 324 319.2 0.48 8.16 re f* 324.48 312 m 324.48 312.24 l 324 312.24 l 324 312 l h f* 324.48 303.84 m 324.48 303.6 l 324 303.6 l 324 303.84 l h f* 324 303.84 0.48 8.16 re f* 324.48 296.88 m 324.48 297.12 l 324 297.12 l 324 296.88 l h f 324.48 293.04 m 324.48 292.8 l 324 292.8 l 324 293.04 l h f 324 293.04 0.48 3.84 re f BT 118.8 354.48 TD 0.0871 Tc (CONTROL) Tj 318 7.2 TD (CONTROL) Tj -105.36 -46.56 TD (CONTROL) Tj 56.64 -38.64 TD 0.1152 Tc (ADR) Tj -14.16 -28.32 TD 0.1182 Tc (RDAT) Tj ET 433.2 246 m 433.2 249.36 l 433.92 249.12 l 443.04 246.48 l 444.72 246 l 443.04 245.52 l 433.92 242.88 l 433.2 242.64 l 433.2 243.36 l 433.68 243.84 l 442.8 246.48 l 443.04 245.52 l 442.8 245.52 l 433.68 248.16 l 433.92 249.12 l 434.16 248.64 l 434.16 246 l h f 433.2 243.36 m 433.2 246 l 434.16 246 l 434.16 243.36 l h f 433.68 246 m 433.68 248.64 l 442.8 246 l 433.68 243.36 l h f* 345.36 245.76 0.24 0.48 re f 433.2 245.76 0.24 0.48 re f 345.6 246.24 m 345.6 245.76 l 433.2 245.76 l 433.2 246.24 l h f BT 388.08 262.32 TD 0.0294 Tc (WDAT) Tj ET 239.04 373.68 m 239.04 377.76 l 239.76 377.52 l 251.76 374.16 l 253.44 373.68 l 251.76 373.2 l 239.76 369.6 l 239.04 369.36 l 239.04 370.08 l 239.52 370.56 l 251.52 374.16 l 251.76 373.2 l 251.52 373.2 l 239.52 376.56 l 239.76 377.52 l 240 377.04 l 240 373.68 l h f 239.04 370.08 m 239.04 373.68 l 240 373.68 l 240 370.08 l h f 239.52 373.68 m 239.52 377.04 l 251.52 373.68 l 239.52 370.08 l h f* 217.44 373.2 0.48 0.96 re f 239.04 373.2 0.48 0.96 re f 217.92 374.16 m 217.92 373.2 l 239.04 373.2 l 239.04 374.16 l h f BT 193.2 369.12 TD 0.0816 Tc (INT) Tj ET endstream endobj 33 0 obj 14915 endobj 31 0 obj << /Type /Page /Parent 28 0 R /Resources << /Font << /F0 6 0 R /F1 8 0 R >> /ProcSet 2 0 R >> /Contents 32 0 R >> endobj 35 0 obj << /Length 36 0 R >> stream BT 77.76 500.88 TD 0 0 0 rg /F1 12 Tf 0.1103 Tc -0.1103 Tw (We call a full T2 cycle an M cycle; most opcodes use only a single M cycle \(M1\), opcodes with) Tj -5.76 -13.92 TD 0.0448 Tc 0.1387 Tw (a short immediate operand require two M cycles \(M1 and M2\), and so on. The longest opcode is) Tj 0 -14.16 TD 0.0632 Tc -0.3663 Tw (RET, reading the return address in M2 and M3, plus 2 M cycles delay from the PC to the excution) Tj 0 -13.92 TD 0.096 Tc 0 Tw (unit.) Tj 5.76 -19.92 TD 0.0185 Tc -0.1385 Tw (... documentation ongoing ...) Tj -5.76 -36 TD /F0 18 Tf 0.12 Tc 0 Tw (5) Tj 56.64 0 TD 0.0327 Tc -0.2127 Tw (Future Plans) Tj -56.64 -31.44 TD /F0 13.92 Tf -0.04 Tc 0 Tw (5.1) Tj 56.64 0 TD 0.0305 Tc -0.0305 Tw (Finalizing the Documentation) Tj -50.88 -18.72 TD /F1 12 Tf 0.0942 Tc 0.2208 Tw (This activity is ongoing. Please feel free to comment what you are missing in the current docu-) Tj -5.76 -13.92 TD 0.072 Tc 0 Tw (mentation.) Tj 0 -29.28 TD /F0 13.92 Tf -0.04 Tc (5.2) Tj 56.64 0 TD -0.0072 Tc 0.1272 Tw (Wishbone Adaptation) Tj -50.88 -18.72 TD /F1 12 Tf 0.093 Tc 0.612 Tw (This should be fairly straight-forward, but I am wondering if there is any interest in this CPU.) Tj -5.76 -13.92 TD 0.0974 Tc -0.2082 Tw (Pleas feel free to comment if you think a Wishbone Adaptation would be worthwhile.) Tj ET 1 1 1 rg 72 536.88 468 171.12 re f 0 0 0 rg 139.68 672.24 0.24 0.48 re f 139.92 672.72 m 161.28 672.72 l 161.52 672.24 l 161.04 672.48 l 168 693.84 l 168 694.08 l 168.24 694.08 l 168.48 693.6 l 161.52 672.24 l 139.92 672.24 l h f 168.24 694.08 m 189.84 694.08 l 189.84 693.84 l 189.6 693.6 l 168.24 693.6 l h f 197.04 672.48 m 197.04 672.24 l 196.56 672 l 196.56 672.24 l h f 189.84 693.84 m 189.36 693.6 l 196.56 672.24 l 197.04 672.48 l h f 196.56 672.24 0.24 0.48 re f 196.8 672.72 m 217.92 672.72 l 218.16 672.24 l 217.68 672.48 l 224.88 693.84 l 224.88 694.08 l 225.12 694.08 l 225.36 693.6 l 218.16 672.24 l 196.8 672.24 l h f 225.12 694.08 m 246.48 694.08 l 246.48 693.84 l 246.24 693.6 l 225.12 693.6 l h f 253.68 672.48 m 253.68 672.24 l 253.2 672 l 253.2 672.24 l h f 246.48 693.84 m 246 693.6 l 253.2 672.24 l 253.68 672.48 l h f 253.2 672.24 0.24 0.48 re f 253.44 672.72 m 274.56 672.72 l 274.8 672.24 l 274.32 672.48 l 281.52 693.84 l 281.52 694.08 l 281.76 694.08 l 282 693.6 l 274.8 672.24 l 253.44 672.24 l h f 281.76 694.08 m 303.12 694.08 l 303.12 693.84 l 302.88 693.6 l 281.76 693.6 l h f 310.32 672.48 m 310.32 672.24 l 309.84 672 l 309.84 672.24 l h f 303.12 693.84 m 302.64 693.6 l 309.84 672.24 l 310.32 672.48 l h f 309.84 672.24 0.24 0.48 re f 310.08 672.72 m 331.44 672.72 l 331.68 672.24 l 331.2 672.48 l 338.16 693.84 l 338.16 694.08 l 338.4 694.08 l 338.64 693.6 l 331.68 672.24 l 310.08 672.24 l h f 338.4 694.08 m 360 694.08 l 360 693.84 l 359.76 693.6 l 338.4 693.6 l h f 366.96 672.48 m 366.96 672.24 l 366.48 672 l 366.48 672.24 l h f 360 693.84 m 359.52 693.6 l 366.48 672.24 l 366.96 672.48 l h f 366.48 672.24 0.24 0.48 re f 366.72 672.72 m 388.08 672.72 l 388.32 672.24 l 387.84 672.48 l 394.8 693.84 l 394.8 694.08 l 395.04 694.08 l 395.28 693.6 l 388.32 672.24 l 366.72 672.24 l h f 395.04 694.08 m 416.64 694.08 l 416.64 693.84 l 416.4 693.6 l 395.04 693.6 l h f 423.6 672.48 m 423.6 672.24 l 423.12 672 l 423.12 672.24 l h f 416.64 693.84 m 416.16 693.6 l 423.12 672.24 l 423.6 672.48 l h f 423.12 672.24 0.24 0.48 re f 423.36 672.72 m 444.72 672.72 l 444.96 672.24 l 444.48 672.48 l 451.68 693.84 l 451.68 694.08 l 451.92 694.08 l 452.16 693.6 l 444.96 672.24 l 423.36 672.24 l h f 451.92 694.08 m 473.28 694.08 l 473.28 693.84 l 473.04 693.6 l 451.92 693.6 l h f 480.48 672.48 m 480.48 672.24 l 480 672 l 480 672.24 l h f 473.28 693.84 m 472.8 693.6 l 480 672.24 l 480.48 672.48 l h f 480 672.24 0.24 0.48 re f 480.24 672.72 m 501.36 672.72 l 501.6 672.24 l 501.12 672.48 l 508.32 693.84 l 508.32 694.08 l 508.56 694.08 l 508.8 693.6 l 501.6 672.24 l 480.24 672.24 l h f 508.56 694.08 m 529.92 694.08 l 529.92 693.84 l 529.68 693.6 l 508.56 693.6 l h f 537.12 672.48 m 537.12 672.24 l 536.64 672 l 536.64 672.24 l h f 529.92 693.84 m 529.44 693.6 l 536.64 672.24 l 537.12 672.48 l h f BT 83.28 677.76 TD /F0 9.84 Tf 0.1952 Tc 0 Tw (CLK) Tj ET 168.72 693.84 m 168.72 694.32 l 167.76 694.32 l 167.76 693.84 l h f 168.72 559.2 m 168.72 558.72 l 167.76 558.72 l 167.76 559.2 l h f 167.76 559.2 0.96 134.64 re f 282.24 693.84 m 282.24 694.32 l 281.28 694.32 l 281.28 693.84 l h f 282.24 559.2 m 282.24 558.72 l 281.28 558.72 l 281.28 559.2 l h f 281.28 559.2 0.96 134.64 re f 395.52 693.84 m 395.52 694.32 l 394.56 694.32 l 394.56 693.84 l h f 395.52 559.2 m 395.52 558.72 l 394.56 558.72 l 394.56 559.2 l h f 394.56 559.2 0.96 134.64 re f 509.04 693.84 m 509.04 694.32 l 508.08 694.32 l 508.08 693.84 l h f 509.04 552 m 509.04 551.52 l 508.08 551.52 l 508.08 552 l h f 508.08 552 0.96 141.84 re f 225.6 693.84 m 225.6 694.32 l 224.64 694.32 l 224.64 693.84 l h f 225.6 690.24 m 225.6 689.76 l 224.64 689.76 l 224.64 690.24 l h f 224.64 690.24 0.96 3.6 re f 225.6 684 m 225.6 684.48 l 224.64 684.48 l 224.64 684 l h f* 225.6 677.52 m 225.6 677.04 l 224.64 677.04 l 224.64 677.52 l h f* 224.64 677.52 0.96 6.48 re f* 225.6 671.04 m 225.6 671.52 l 224.64 671.52 l 224.64 671.04 l h f* 225.6 664.56 m 225.6 664.08 l 224.64 664.08 l 224.64 664.56 l h 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