head	1.2;
access;
symbols
	mkfiles_rev1:1.1.0.2;
locks; strict;
comment	@# @;


1.2
date	2008.08.20.06.01.01;	author davidgb;	state Exp;
branches;
next	1.1;
commitid	103148abb2444567;

1.1
date	2008.04.07.18.45.09;	author davidgb;	state dead;
branches
	1.1.2.1;
next	;
commitid	485347fa6bb04567;

1.1.2.1
date	2008.04.07.18.45.09;	author davidgb;	state Exp;
branches;
next	;
commitid	485347fa6bb04567;


desc
@@


1.2
log
@merged mkfiles_rev1 branch to the mainline
@
text
@--
-- Flex9 O/S Initialised 8KByte RAM
--
-- v1.0 - 22 December 2006 - John Kent
-- v1.1 -  1 February 2008 - David Burnette
--        reworked to use autogenerated block ram utility

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
	use unisim.vcomponents.all;

entity flex_ram is
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (12 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
    );
end flex_ram;

architecture rtl of flex_ram is

  signal we     : std_logic;
  signal cs0    : std_logic;
  signal cs1    : std_logic;
  signal cs2    : std_logic;
  signal cs3    : std_logic;
  signal dp0    : std_logic;
  signal dp1    : std_logic;
  signal dp2    : std_logic;
  signal dp3    : std_logic;
  signal rdata0 : std_logic_vector(7 downto 0);
  signal rdata1 : std_logic_vector(7 downto 0);
  signal rdata2 : std_logic_vector(7 downto 0);
  signal rdata3 : std_logic_vector(7 downto 0);

component FLEX9_C000
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
    );
end component;
component FLEX9_C800
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
    );
end component;
component FLEX9_D000
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
    );
end component;
component FLEX9_D800
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
    );
end component;

begin

   addr_c000 : FLEX9_C000 port map (
       clk   => clk,
       rst   => rst,
       cs    => cs0,
       rw    => rw,
       addr  => addr(10 downto 0),
       wdata => wdata,
       rdata => rdata0
    );

   addr_c800 : FLEX9_C800 port map (
       clk   => clk,
       rst   => rst,
       cs    => cs1,
       rw    => rw,
       addr  => addr(10 downto 0),
       wdata => wdata,
       rdata => rdata1
    );
   addr_d000 : FLEX9_D000 port map (
       clk   => clk,
       rst   => rst,
       cs    => cs2,
       rw    => rw,
       addr  => addr(10 downto 0),
       wdata => wdata,
       rdata => rdata2
    );
   addr_d800 : FLEX9_D800 port map (
       clk   => clk,
       rst   => rst,
       cs    => cs3,
       rw    => rw,
       addr  => addr(10 downto 0),
       wdata => wdata,
       rdata => rdata3
    );

my_flex : process ( rw, addr, cs, rdata0, rdata1, rdata2, rdata3 )
begin
	 we    <= not rw;
	 case addr(12 downto 11) is
	 when "00" =>
		cs0   <= cs;
		cs1   <= '0';
		cs2   <= '0';
		cs3   <= '0';
		rdata <= rdata0;
    when "01" =>
		cs0   <= '0';
		cs1   <= cs;
		cs2   <= '0';
		cs3   <= '0';
		rdata <= rdata1;
	 when "10" =>
		cs0   <= '0';
		cs1   <= '0';
		cs2   <= cs;
		cs3   <= '0';
		rdata <= rdata2;
    when "11" =>
		cs0   <= '0';
		cs1   <= '0';
		cs2   <= '0';
		cs3   <= cs;
		rdata <= rdata3;
    when others =>
		null;
    end case;		
		
end process;

end architecture rtl;

@


1.1
log
@file flex_ram_vhd was initially added on branch mkfiles_rev1.
@
text
@d1 162
@


1.1.2.1
log
@Overlay makefiles. Renamed some 6809 assembler source files from
.txt to .asm (and updated the shell scripts).
Fixed xess .UCF file to work with ISE 9.2i.
Added missing sdram VHD files for Xess board.
All work is on the mkfiles_rev1 branch.
@
text
@a0 162
--
-- Flex9 O/S Initialised 8KByte RAM
--
-- v1.0 - 22 December 2006 - John Kent
-- v1.1 -  1 February 2008 - David Burnette
--        reworked to use autogenerated block ram utility

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
library unisim;
	use unisim.vcomponents.all;

entity flex_ram is
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (12 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
    );
end flex_ram;

architecture rtl of flex_ram is

  signal we     : std_logic;
  signal cs0    : std_logic;
  signal cs1    : std_logic;
  signal cs2    : std_logic;
  signal cs3    : std_logic;
  signal dp0    : std_logic;
  signal dp1    : std_logic;
  signal dp2    : std_logic;
  signal dp3    : std_logic;
  signal rdata0 : std_logic_vector(7 downto 0);
  signal rdata1 : std_logic_vector(7 downto 0);
  signal rdata2 : std_logic_vector(7 downto 0);
  signal rdata3 : std_logic_vector(7 downto 0);

component FLEX9_C000
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
    );
end component;
component FLEX9_C800
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
    );
end component;
component FLEX9_D000
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
    );
end component;
component FLEX9_D800
    Port (
       clk   : in  std_logic;
       rst   : in  std_logic;
       cs    : in  std_logic;
       rw    : in  std_logic;
       addr  : in  std_logic_vector (10 downto 0);
       rdata : out std_logic_vector (7 downto 0);
       wdata : in  std_logic_vector (7 downto 0)
    );
end component;

begin

   addr_c000 : FLEX9_C000 port map (
       clk   => clk,
       rst   => rst,
       cs    => cs0,
       rw    => rw,
       addr  => addr(10 downto 0),
       wdata => wdata,
       rdata => rdata0
    );

   addr_c800 : FLEX9_C800 port map (
       clk   => clk,
       rst   => rst,
       cs    => cs1,
       rw    => rw,
       addr  => addr(10 downto 0),
       wdata => wdata,
       rdata => rdata1
    );
   addr_d000 : FLEX9_D000 port map (
       clk   => clk,
       rst   => rst,
       cs    => cs2,
       rw    => rw,
       addr  => addr(10 downto 0),
       wdata => wdata,
       rdata => rdata2
    );
   addr_d800 : FLEX9_D800 port map (
       clk   => clk,
       rst   => rst,
       cs    => cs3,
       rw    => rw,
       addr  => addr(10 downto 0),
       wdata => wdata,
       rdata => rdata3
    );

my_flex : process ( rw, addr, cs, rdata0, rdata1, rdata2, rdata3 )
begin
	 we    <= not rw;
	 case addr(12 downto 11) is
	 when "00" =>
		cs0   <= cs;
		cs1   <= '0';
		cs2   <= '0';
		cs3   <= '0';
		rdata <= rdata0;
    when "01" =>
		cs0   <= '0';
		cs1   <= cs;
		cs2   <= '0';
		cs3   <= '0';
		rdata <= rdata1;
	 when "10" =>
		cs0   <= '0';
		cs1   <= '0';
		cs2   <= cs;
		cs3   <= '0';
		rdata <= rdata2;
    when "11" =>
		cs0   <= '0';
		cs1   <= '0';
		cs2   <= '0';
		cs3   <= cs;
		rdata <= rdata3;
    when others =>
		null;
    end case;		
		
end process;

end architecture rtl;

@