head 1.1; branch 1.1.1; access; symbols arelease:1.1.1.2 avendor:1.1.1; locks; strict; comment @# @; 1.1 date 2002.03.07.19.05.49; author victor; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2002.03.07.19.05.49; author victor; state Exp; branches; next 1.1.1.2; 1.1.1.2 date 2002.05.16.19.26.26; author victor; state Exp; branches; next ; desc @@ 1.1 log @Initial revision @ text @PACKAGE constants IS constant G711_DATA_HIGH: INTEGER := 12; constant G711_OUT_HIGH: INTEGER := 7; END constants; library ieee; use ieee.std_logic_1164.all; USE ieee.std_logic_arith.all; USE ieee.std_logic_unsigned.all; LIBRARY lpm; USE lpm.lpm_components.all; LIBRARY work; USE work.constants.all; entity G711 is port(PCM_in: in std_logic_vector(G711_DATA_HIGH downto 0); G711_in: in std_logic_vector(G711_OUT_HIGH downto 0); PCM_out: out std_logic_vector(G711_DATA_HIGH downto 0); G711_out:out std_logic_vector(G711_OUT_HIGH downto 0) ); end G711; architecture BEHAVIOR of G711 is signal seg,seg_d: STD_LOGIC_VECTOR (2 downto 0); signal G711_ins: STD_LOGIC_VECTOR (G711_OUT_HIGH downto 0); signal sub_wire0,PCM_in1:STD_LOGIC_VECTOR(10 downto 0); SIGNAL sub_wire3 : STD_LOGIC_VECTOR (11 DOWNTO 0); SIGNAL sub_wire2 : STD_LOGIC ; --this component added because of progect needs 2 clshifts with dufferent data range COMPONENT shift PORT ( distance : IN STD_LOGIC_VECTOR (2 DOWNTO 0); data : IN STD_LOGIC_VECTOR (10 DOWNTO 0); result : OUT STD_LOGIC_VECTOR (10 DOWNTO 0) ); END COMPONENT; COMPONENT lpm_clshift GENERIC ( LPM_SHIFTTYPE : STRING; LPM_WIDTH : NATURAL; LPM_WIDTHDIST : NATURAL ); PORT ( distance : IN STD_LOGIC_VECTOR (2 DOWNTO 0); direction : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR (11 DOWNTO 0); result : OUT STD_LOGIC_VECTOR (11 DOWNTO 0) ); END COMPONENT; begin -- encoder -- segment calculation, logic function build in accordance with ITU-T G.711 A-Law (Table 1a/1b) seg(0)<=PCM_in(11) or (not(PCM_in(10)) AND PCM_in(9)) or (not(PCM_in(8)) and not(PCM_in(10)) and PCM_in(7)) or (not(PCM_in(6)) and not(PCM_in(8)) and not(PCM_in(10))); --seg(0)<=(not(seg(2) and seg(1)) or PCM_in(11)) and (not(seg(2)) or seg(1) or PCM_in(9)) and (seg(2) or not(seg(1)) or PCM_in(7)); seg(1)<=PCM_in(11) or PCM_in(10) or (not(PCM_in(9)) and not(PCM_in(8)) and (PCM_in(7) or PCM_in(6))); seg(2)<=PCM_in(11) or PCM_in(10) or PCM_in(9) or PCM_in(8); PCM_in1(10 downto 1)<=PCM_in(10 downto 1); PCM_in1(0)<=PCM_in(11); -- shifting lpm_1 : shift PORT MAP ( distance => seg, data => PCM_in1, result => sub_wire0 ); -- linking output code G711_out(3 downto 0)<= (sub_wire0(3 downto 0)) xor "0101"; G711_out(5)<=seg(1); G711_out(6)<=not(seg(2)); G711_out(7)<=not(PCM_in(12)); G711_out(4)<= not((seg(0) and (seg(1) or seg(2))) or (sub_wire0(4)and not(seg(1) or seg(2)))); --decoder part sub_wire2 <= '0'; lpm_2 : lpm_clshift GENERIC MAP ( LPM_SHIFTTYPE => "ROTATE", LPM_WIDTH => 12, LPM_WIDTHDIST => 3 ) PORT MAP ( distance => seg_d, direction => sub_wire2, data => sub_wire3, result => PCM_out(11 downto 0) ); G711_ins<=G711_in xor "11010101"; --shift calculation seg_d(2)<=G711_ins(6); seg_d(1)<=G711_ins(5); seg_d(0)<=not(G711_ins(6) or G711_ins(5)) or G711_ins(4); --prepare for shifting sub_wire3(3 downto 0)<=G711_ins(3 downto 0); sub_wire3(4)<=G711_ins(6) or G711_ins(5) or G711_ins(4); sub_wire3(10 downto 5)<="0000000"; sub_wire3(11)<='1';-- this is the main feature use ROTATE not ARITHMETIC!! PCM_out(12)<=G711_ins(7); end BEHAVIOR; @ 1.1.1.1 log @no message @ text @@ 1.1.1.2 log @no message @ text @a0 36 ---- ---- ---- This file is part of the G711 a-law project ---- ---- http://www.opencores.org/cores/G711/ ---- ---- Description: ITU-T G.711 a-law codec, main module ---- Implementation of G711 a-law IP core according to ---- ---- G711 a-law IP core specification document. ---- ---- Author(s): Tokarev Victor ---- e-mail: victor@@opencores.org ---- ---- ---- ---------------------------------------------------------------------- ---- ---- ---- Copyright (C) 2002 Authors and OPENCORES.ORG ---- ---- ---- ---- This source file may be used and distributed without ---- ---- restriction provided that this copyright statement is not ---- ---- removed from the file and that any derivative work contains ---- ---- the original copyright notice and the associated disclaimer. ---- ---- ---- ---- This source file is free software; you can redistribute it ---- ---- and/or modify it under the terms of the GNU Lesser General ---- ---- Public License as published by the Free Software Foundation; ---- ---- either version 2.1 of the License, or (at your option) any ---- ---- later version. ---- ---- ---- ---- This source is distributed in the hope that it will be ---- ---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ---- PURPOSE. See the GNU Lesser General Public License for more ---- ---- details. ---- ---- ---- ---- You should have received a copy of the GNU Lesser General ---- ---- Public License along with this source; if not, download it ---- ---- from http://www.opencores.org/lgpl.shtml ---- ---- ---- ---------------------------------------------------------------------- d10 2 a11 1 d26 1 a26 2 signal sub_wire0: STD_LOGIC_VECTOR(4 downto 0); signal PCM_in1:STD_LOGIC_VECTOR(10 downto 0); d28 1 d30 1 d36 1 a36 1 result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0) d41 6 a46 1 COMPONENT shift1 d49 1 d61 1 d85 8 a92 1 lpm_2 : shift1 d95 1 d109 3 a111 2 sub_wire3(10 downto 5)<="000000"; sub_wire3(11)<='1'; @