head 1.1; branch 1.1.1; access; symbols arelease:1.1.1.1 avendor:1.1.1; locks; strict; comment @# @; 1.1 date 2002.03.10.20.32.00; author victor; state Exp; branches 1.1.1.1; next ; 1.1.1.1 date 2002.03.10.20.32.00; author victor; state Exp; branches; next ; desc @@ 1.1 log @Initial revision @ text @Project Information c:\study\vhdl\codecs\g711.3\g711.rpt MAX+plus II Compiler Report File Version 9.4 12/10/1999 Compiled: 03/07/2002 21:52:58 Copyright (C) 1988-1999 Altera Corporation Any megafunction design, and related net list (encrypted or decrypted), support information, device programming or simulation file, and any other associated documentation or information provided by Altera or a partner under Altera's Megafunction Partnership Program may be used only to program PLD devices (but not masked PLD devices) from Altera. Any other use of such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information is prohibited for any other purpose, including, but not limited to modification, reverse engineering, de-compiling, or use with any other silicon devices, unless such use is explicitly licensed under a separate agreement with Altera or a megafunction partner. Title to the intellectual property, including patents, copyrights, trademarks, trade secrets, or maskworks, embodied in any such megafunction design, net list, support information, device programming or simulation file, or any other related documentation or information provided by Altera or a megafunction partner, remains with Altera, the megafunction partner, or their respective licensors. No other licenses, including any licenses needed under any third party's intellectual property, are provided herein. ***** Project compilation was successful G711 ** DEVICE SUMMARY ** Chip/ Input Output Bidir Memory Memory LCs POF Device Pins Pins Pins Bits % Utilized LCs % Utilized g711 EPF10K10LC84-3 20 21 0 0 0 % 52 9 % User Pins: 20 21 0 Project Information c:\study\vhdl\codecs\g711.3\g711.rpt ** PROJECT COMPILATION MESSAGES ** Warning: Ignored unnecessary INPUT pin 'PCM_in0' Project Information c:\study\vhdl\codecs\g711.3\g711.rpt ** FILE HIERARCHY ** |shift:lpm_1| |shift:lpm_1|lpm_clshift:lpm_clshift_component| |lpm_clshift:lpm_2| Device-Specific Information: c:\study\vhdl\codecs\g711.3\g711.rpt g711 ***** Logic for device 'g711' compiled without errors. Device: EPF10K10LC84-3 FLEX 10K Configuration Scheme: Passive Serial Device Options: User-Supplied Start-Up Clock = OFF Auto-Restart Configuration on Frame Error = OFF Release Clears Before Tri-States = OFF Enable Chip_Wide Reset = OFF Enable Chip-Wide Output Enable = OFF Enable INIT_DONE Output = OFF JTAG User Code = 7f ^ G G G C P P P 7 P 7 7 R G G R R R R R O C C C 1 C 1 1 E 7 P 7 E E E E E N M M M 1 M 1 1 V S 1 C 1 S G S S S S F _ _ _ _ _ _ _ C E 1 M 1 E N E E E E _ ^ o o o o o o o C R _ _ _ R D R R R R # D n u u u u u u u I V i i i V I V V V V T O C t t t t t t t N E n n n E N E E E E C N E 6 8 5 1 3 3 5 T D 6 6 5 D T D D D D K E O -----------------------------------------------------------------_ / 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 | ^DATA0 | 12 74 | #TDO ^DCLK | 13 73 | PCM_in9 ^nCE | 14 72 | PCM_in10 #TDI | 15 71 | PCM_in11 PCM_in3 | 16 70 | PCM_in5 PCM_in2 | 17 69 | PCM_in4 PCM_in1 | 18 68 | GNDINT G711_out6 | 19 67 | G711_in0 VCCINT | 20 66 | G711_in3 PCM_out4 | 21 65 | G711_in2 PCM_out0 | 22 EPF10K10LC84-3 64 | G711_in1 G711_out4 | 23 63 | VCCINT G711_out0 | 24 62 | G711_in7 PCM_out2 | 25 61 | PCM_in12 GNDINT | 26 60 | G711_out7 RESERVED | 27 59 | PCM_out10 PCM_out9 | 28 58 | PCM_out1 PCM_out12 | 29 57 | #TMS PCM_out7 | 30 56 | #TRST ^MSEL0 | 31 55 | ^nSTATUS ^MSEL1 | 32 54 | RESERVED |_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _| ------------------------------------------------------------------ V ^ G R P R R V G G P P V G R R R R R R R C n 7 E C E E C N 7 C C C N E E E E E E E C C 1 S M S S C D 1 M M C D S S S S S S S I O 1 E _ E E I I 1 _ _ I I E E E E E E E N N _ R o R R N N _ i i N N R R R R R R R T F o V u V V T T i n n T T V V V V V V V I u E t E E n 7 8 E E E E E E E G t D 1 D D 4 D D D D D D D 2 1 N.C. = No Connect. This pin has no internal connection to the device. VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts). VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts). GNDINT = Dedicated ground pin or unused dedicated input, which MUST be connected to GND. GNDIO = Dedicated ground pin, which MUST be connected to GND. RESERVED = Unused I/O pin, which MUST be left unconnected. ^ = Dedicated configuration pin. + = Reserved configuration pin, which is tri-stated during user mode. * = Reserved configuration pin, which drives out in user mode. PDn = Power Down pin. @@ = Special-purpose pin. # = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use. & = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions. Device-Specific Information: c:\study\vhdl\codecs\g711.3\g711.rpt g711 ** RESOURCE USAGE ** Logic Column Row Array Interconnect Interconnect Clears/ External Block Logic Cells Driven Driven Clocks Presets Interconnect A4 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 10/22( 45%) A5 8/ 8(100%) 2/ 8( 25%) 0/ 8( 0%) 0/2 0/2 10/22( 45%) A6 4/ 8( 50%) 2/ 8( 25%) 1/ 8( 12%) 0/2 0/2 9/22( 40%) A7 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%) A8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%) A9 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%) A10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%) A11 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 6/22( 27%) A12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 3/22( 13%) B1 8/ 8(100%) 2/ 8( 25%) 2/ 8( 25%) 0/2 0/2 8/22( 36%) B2 8/ 8(100%) 3/ 8( 37%) 1/ 8( 12%) 0/2 0/2 8/22( 36%) B3 3/ 8( 37%) 3/ 8( 37%) 0/ 8( 0%) 0/2 0/2 5/22( 22%) B8 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 2/22( 9%) B9 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 0/2 0/2 3/22( 13%) B12 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 4/22( 18%) C10 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) C13 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%) Embedded Column Row Array Embedded Interconnect Interconnect Read/ External Block Cells Driven Driven Clocks Write Interconnect Total dedicated input pins used: 6/6 (100%) Total I/O pins used: 35/53 ( 66%) Total logic cells used: 52/576 ( 9%) Total embedded cells used: 0/24 ( 0%) Total EABs used: 0/3 ( 0%) Average fan-in: 3.13/4 ( 78%) Total fan-in: 163/2304 ( 7%) Total input pins required: 20 Total input I/O cell registers required: 0 Total output pins required: 21 Total output I/O cell registers required: 0 Total buried I/O cell registers required: 0 Total bidirectional pins required: 0 Total reserved pins required 0 Total logic cells required: 52 Total flipflops required: 0 Total packed registers required: 0 Total logic cells in carry chains: 0 Total number of carry chains: 0 Total logic cells in cascade chains: 0 Total number of cascade chains: 0 Total single-pin Clock Enables required: 0 Total single-pin Output Enables required: 0 Synthesized logic cells: 3/ 576 ( 0%) Logic Cell and Embedded Cell Counts Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC) A: 0 0 0 8 8 4 1 1 1 1 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 28/0 B: 8 8 3 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 22/0 C: 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 2/0 Total: 8 8 3 8 8 4 1 2 2 2 3 2 0 1 0 0 0 0 0 0 0 0 0 0 0 52/0 Device-Specific Information: c:\study\vhdl\codecs\g711.3\g711.rpt g711 ** INPUTS ** Fan-In Fan-Out Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name 67 - - B -- INPUT 0 0 0 2 G711_in0 64 - - B -- INPUT 0 0 0 2 G711_in1 65 - - B -- INPUT 0 0 0 2 G711_in2 66 - - B -- INPUT 0 0 0 2 G711_in3 42 - - - -- INPUT 0 0 0 10 G711_in4 84 - - - -- INPUT 0 0 0 15 G711_in5 2 - - - -- INPUT 0 0 0 14 G711_in6 62 - - C -- INPUT 0 0 0 1 G711_in7 18 - - A -- INPUT 0 0 0 2 PCM_in1 17 - - A -- INPUT 0 0 0 2 PCM_in2 16 - - A -- INPUT 0 0 0 2 PCM_in3 69 - - A -- INPUT 0 0 0 2 PCM_in4 70 - - A -- INPUT 0 0 0 3 PCM_in5 1 - - - -- INPUT 0 0 0 5 PCM_in6 43 - - - -- INPUT 0 0 0 5 PCM_in7 44 - - - -- INPUT 0 0 0 5 PCM_in8 73 - - A -- INPUT 0 0 0 5 PCM_in9 72 - - A -- INPUT 0 0 0 4 PCM_in10 71 - - A -- INPUT 0 0 0 4 PCM_in11 61 - - C -- INPUT 0 0 0 1 PCM_in12 Code: s = Synthesized pin or logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell @@ = Uses single-pin Clock Enable & = Uses single-pin Output Enable Device-Specific Information: c:\study\vhdl\codecs\g711.3\g711.rpt g711 ** OUTPUTS ** Fed By Fed By Fan-In Fan-Out Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name 24 - - B -- OUTPUT 0 1 0 0 G711_out0 8 - - - 03 OUTPUT 0 1 0 0 G711_out1 35 - - - 06 OUTPUT 0 1 0 0 G711_out2 6 - - - 04 OUTPUT 0 1 0 0 G711_out3 23 - - B -- OUTPUT 0 1 0 0 G711_out4 5 - - - 05 OUTPUT 0 1 0 0 G711_out5 19 - - A -- OUTPUT 0 1 0 0 G711_out6 60 - - C -- OUTPUT 0 1 0 0 G711_out7 22 - - B -- OUTPUT 0 1 0 0 PCM_out0 58 - - C -- OUTPUT 0 1 0 0 PCM_out1 25 - - B -- OUTPUT 0 1 0 0 PCM_out2 7 - - - 03 OUTPUT 0 1 0 0 PCM_out3 21 - - B -- OUTPUT 0 1 0 0 PCM_out4 9 - - - 02 OUTPUT 0 1 0 0 PCM_out5 11 - - - 01 OUTPUT 0 1 0 0 PCM_out6 30 - - C -- OUTPUT 0 1 0 0 PCM_out7 10 - - - 01 OUTPUT 0 1 0 0 PCM_out8 28 - - C -- OUTPUT 0 1 0 0 PCM_out9 59 - - C -- OUTPUT 0 1 0 0 PCM_out10 37 - - - 09 OUTPUT 0 1 0 0 PCM_out11 29 - - C -- OUTPUT 0 1 0 0 PCM_out12 Code: s = Synthesized pin or logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell @@ = Uses single-pin Clock Enable & = Uses single-pin Output Enable Device-Specific Information: c:\study\vhdl\codecs\g711.3\g711.rpt g711 ** BURIED LOGIC ** Fan-In Fan-Out IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name - 4 - C 13 LCELL s 1 0 1 0 G711_out7~1 - 5 - B 01 OR2 4 0 0 2 |lpm_clshift:lpm_2|sbit1_0 - 8 - B 02 OR2 3 1 0 2 |lpm_clshift:lpm_2|sbit1_1 - 7 - B 01 OR2 3 1 0 3 |lpm_clshift:lpm_2|sbit1_2 - 5 - B 02 OR2 3 1 0 2 |lpm_clshift:lpm_2|sbit1_3 - 1 - B 12 OR2 4 0 0 4 |lpm_clshift:lpm_2|sbit1_4 - 4 - B 02 OR2 2 1 0 2 |lpm_clshift:lpm_2|sbit2_1 - 6 - B 01 OR2 1 2 0 2 |lpm_clshift:lpm_2|sbit2_2 - 2 - B 02 OR2 1 2 0 2 |lpm_clshift:lpm_2|sbit2_3 - 3 - B 01 OR2 1 2 0 1 |lpm_clshift:lpm_2|sbit2_4 - 7 - B 02 OR2 2 1 0 2 |lpm_clshift:lpm_2|sbit2_5 - 1 - B 03 OR2 3 1 1 0 |lpm_clshift:lpm_2|sbit3_3 - 1 - B 01 OR2 2 2 1 0 |lpm_clshift:lpm_2|sbit3_4 - 1 - B 02 OR2 1 2 1 0 |lpm_clshift:lpm_2|sbit3_5 - 2 - B 01 OR2 2 2 1 0 |lpm_clshift:lpm_2|sbit3_6 - 7 - B 03 OR2 3 1 1 0 |lpm_clshift:lpm_2|sbit3_7 - 4 - B 01 OR2 2 2 1 0 |lpm_clshift:lpm_2|:353 - 3 - B 02 AND2 1 1 1 0 |lpm_clshift:lpm_2|:354 - 5 - B 03 AND2 2 1 1 0 |lpm_clshift:lpm_2|:355 - 1 - B 09 AND2 3 0 1 0 |lpm_clshift:lpm_2|:356 - 6 - B 02 AND2 1 1 1 0 |lpm_clshift:lpm_2|:396 - 8 - B 01 AND2 1 1 1 0 |lpm_clshift:lpm_2|:398 - 5 - C 10 LCELL s 1 0 1 0 PCM_out12~1 - 8 - A 04 OR2 2 1 0 1 |shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit1_1 - 8 - A 05 OR2 ! 2 1 0 2 |shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit1_2 - 7 - A 04 OR2 2 1 0 2 |shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit1_3 - 7 - A 05 OR2 ! 2 1 0 2 |shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit1_4 - 8 - A 12 OR2 2 1 0 2 |shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit1_5 - 1 - A 08 OR2 ! 2 1 0 2 |shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit1_6 - 1 - A 09 OR2 2 1 0 2 |shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit1_7 - 1 - A 10 OR2 ! 2 1 0 1 |shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit1_8 - 1 - A 11 OR2 3 1 0 1 |shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit1_9 - 2 - A 05 OR2 ! 1 3 0 1 |shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit2_0 - 3 - A 04 OR2 0 3 0 1 |shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit2_1 - 3 - A 05 OR2 ! 0 3 0 1 |shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit2_2 - 4 - A 04 OR2 0 3 0 1 |shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit2_3 - 4 - A 05 OR2 ! 0 3 0 1 |shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit2_4 - 5 - A 04 OR2 0 3 0 1 |shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit2_5 - 5 - A 05 OR2 ! 0 3 0 1 |shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit2_6 - 6 - A 04 OR2 0 3 0 1 |shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit2_7 - 6 - A 05 OR2 ! 0 3 1 0 |shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit3_0 - 2 - A 04 OR2 0 3 1 0 |shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit3_1 - 1 - A 05 OR2 ! 0 3 1 0 |shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit3_2 - 1 - A 04 OR2 0 3 1 0 |shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit3_3 - 3 - A 11 OR2 s 3 0 0 1 ~437~1 - 2 - A 11 OR2 ! 3 1 0 11 :437 - 4 - A 06 OR2 4 0 0 1 :455 - 1 - A 06 OR2 2 1 1 8 :456 - 7 - A 07 AND2 ! 4 0 1 5 :469 - 2 - A 06 OR2 2 1 0 1 :514 - 3 - A 06 OR2 ! 1 2 1 0 :522 - 2 - B 08 AND2 ! 2 0 1 3 :783 Code: s = Synthesized pin or logic cell + = Synchronous flipflop / = Slow slew-rate output ! = NOT gate push-back r = Fitter-inserted logic cell p = Packed register Device-Specific Information: c:\study\vhdl\codecs\g711.3\g711.rpt g711 ** FASTTRACK INTERCONNECT UTILIZATION ** Row FastTrack Interconnect: Global Left Half- Right Half- FastTrack FastTrack FastTrack Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins A: 8/ 96( 8%) 8/ 48( 16%) 0/ 48( 0%) 8/16( 50%) 1/16( 6%) 0/16( 0%) B: 4/ 96( 4%) 7/ 48( 14%) 0/ 48( 0%) 4/16( 25%) 5/16( 31%) 0/16( 0%) C: 4/ 96( 4%) 3/ 48( 6%) 1/ 48( 2%) 2/16( 12%) 6/16( 37%) 0/16( 0%) Column FastTrack Interconnect: FastTrack Column Interconnect Input Pins Output Pins Bidir Pins 01: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%) 02: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 03: 4/24( 16%) 0/4( 0%) 2/4( 50%) 0/4( 0%) 04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 05: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%) 10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) 24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%) Device-Specific Information: c:\study\vhdl\codecs\g711.3\g711.rpt g711 ** EQUATIONS ** G711_in0 : INPUT; G711_in1 : INPUT; G711_in2 : INPUT; G711_in3 : INPUT; G711_in4 : INPUT; G711_in5 : INPUT; G711_in6 : INPUT; G711_in7 : INPUT; PCM_in1 : INPUT; PCM_in2 : INPUT; PCM_in3 : INPUT; PCM_in4 : INPUT; PCM_in5 : INPUT; PCM_in6 : INPUT; PCM_in7 : INPUT; PCM_in8 : INPUT; PCM_in9 : INPUT; PCM_in10 : INPUT; PCM_in11 : INPUT; PCM_in12 : INPUT; -- Node name is 'G711_out0' -- Equation name is 'G711_out0', type is output G711_out0 = !_LC6_A5; -- Node name is 'G711_out1' -- Equation name is 'G711_out1', type is output G711_out1 = _LC2_A4; -- Node name is 'G711_out2' -- Equation name is 'G711_out2', type is output G711_out2 = !_LC1_A5; -- Node name is 'G711_out3' -- Equation name is 'G711_out3', type is output G711_out3 = _LC1_A4; -- Node name is 'G711_out4' -- Equation name is 'G711_out4', type is output G711_out4 = !_LC3_A6; -- Node name is 'G711_out5' -- Equation name is 'G711_out5', type is output G711_out5 = _LC1_A6; -- Node name is 'G711_out6' -- Equation name is 'G711_out6', type is output G711_out6 = !_LC7_A7; -- Node name is 'G711_out7~1' -- Equation name is 'G711_out7~1', location is LC4_C13, type is buried. -- synthesized logic cell _LC4_C13 = LCELL( PCM_in12); -- Node name is 'G711_out7' -- Equation name is 'G711_out7', type is output G711_out7 = !_LC4_C13; -- Node name is 'PCM_out0' -- Equation name is 'PCM_out0', type is output PCM_out0 = !_LC2_B8; -- Node name is 'PCM_out1' -- Equation name is 'PCM_out1', type is output PCM_out1 = _LC6_B2; -- Node name is 'PCM_out2' -- Equation name is 'PCM_out2', type is output PCM_out2 = _LC8_B1; -- Node name is 'PCM_out3' -- Equation name is 'PCM_out3', type is output PCM_out3 = _LC1_B3; -- Node name is 'PCM_out4' -- Equation name is 'PCM_out4', type is output PCM_out4 = _LC1_B1; -- Node name is 'PCM_out5' -- Equation name is 'PCM_out5', type is output PCM_out5 = _LC1_B2; -- Node name is 'PCM_out6' -- Equation name is 'PCM_out6', type is output PCM_out6 = _LC2_B1; -- Node name is 'PCM_out7' -- Equation name is 'PCM_out7', type is output PCM_out7 = _LC7_B3; -- Node name is 'PCM_out8' -- Equation name is 'PCM_out8', type is output PCM_out8 = _LC4_B1; -- Node name is 'PCM_out9' -- Equation name is 'PCM_out9', type is output PCM_out9 = _LC3_B2; -- Node name is 'PCM_out10' -- Equation name is 'PCM_out10', type is output PCM_out10 = _LC5_B3; -- Node name is 'PCM_out11' -- Equation name is 'PCM_out11', type is output PCM_out11 = _LC1_B9; -- Node name is 'PCM_out12~1' -- Equation name is 'PCM_out12~1', location is LC5_C10, type is buried. -- synthesized logic cell _LC5_C10 = LCELL( G711_in7); -- Node name is 'PCM_out12' -- Equation name is 'PCM_out12', type is output PCM_out12 = !_LC5_C10; -- Node name is '|lpm_clshift:lpm_2|sbit1_0' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC5_B1', type is buried _LC5_B1 = LCELL( _EQ001); _EQ001 = !G711_in5 & G711_in6 # !G711_in4 # !G711_in0; -- Node name is '|lpm_clshift:lpm_2|sbit1_1' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC8_B2', type is buried _LC8_B2 = LCELL( _EQ002); _EQ002 = G711_in1 & G711_in4 & _LC2_B8 # !G711_in0 & !G711_in4 # !G711_in0 & !_LC2_B8; -- Node name is '|lpm_clshift:lpm_2|sbit1_2' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC7_B1', type is buried _LC7_B1 = LCELL( _EQ003); _EQ003 = !G711_in2 & G711_in4 & _LC2_B8 # G711_in1 & !G711_in4 # G711_in1 & !_LC2_B8; -- Node name is '|lpm_clshift:lpm_2|sbit1_3' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC5_B2', type is buried _LC5_B2 = LCELL( _EQ004); _EQ004 = G711_in3 & G711_in4 & _LC2_B8 # !G711_in2 & !G711_in4 # !G711_in2 & !_LC2_B8; -- Node name is '|lpm_clshift:lpm_2|sbit1_4' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC1_B12', type is buried _LC1_B12 = LCELL( _EQ005); _EQ005 = G711_in3 & !G711_in5 & G711_in6 # G711_in3 & !G711_in4 # G711_in4 & G711_in5 # G711_in4 & !G711_in6; -- Node name is '|lpm_clshift:lpm_2|sbit2_1' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC4_B2', type is buried _LC4_B2 = LCELL( _EQ006); _EQ006 = !G711_in5 & _LC8_B2 # G711_in4 & G711_in5; -- Node name is '|lpm_clshift:lpm_2|sbit2_2' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC6_B1', type is buried _LC6_B1 = LCELL( _EQ007); _EQ007 = G711_in5 & _LC5_B1 # !G711_in5 & _LC7_B1; -- Node name is '|lpm_clshift:lpm_2|sbit2_3' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC2_B2', type is buried _LC2_B2 = LCELL( _EQ008); _EQ008 = !G711_in5 & _LC5_B2 # G711_in5 & _LC8_B2; -- Node name is '|lpm_clshift:lpm_2|sbit2_4' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC3_B1', type is buried _LC3_B1 = LCELL( _EQ009); _EQ009 = !G711_in5 & _LC1_B12 # G711_in5 & _LC7_B1; -- Node name is '|lpm_clshift:lpm_2|sbit2_5' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC7_B2', type is buried _LC7_B2 = LCELL( _EQ010); _EQ010 = !G711_in4 & !G711_in5 # G711_in5 & _LC5_B2; -- Node name is '|lpm_clshift:lpm_2|sbit3_3' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC1_B3', type is buried _LC1_B3 = LCELL( _EQ011); _EQ011 = G711_in6 & _LC2_B2 # G711_in4 & !G711_in5 & !G711_in6; -- Node name is '|lpm_clshift:lpm_2|sbit3_4' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC1_B1', type is buried _LC1_B1 = LCELL( _EQ012); _EQ012 = G711_in6 & _LC3_B1 # !G711_in5 & !G711_in6 & _LC5_B1; -- Node name is '|lpm_clshift:lpm_2|sbit3_5' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC1_B2', type is buried _LC1_B2 = LCELL( _EQ013); _EQ013 = !G711_in6 & _LC4_B2 # G711_in6 & _LC7_B2; -- Node name is '|lpm_clshift:lpm_2|sbit3_6' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC2_B1', type is buried _LC2_B1 = LCELL( _EQ014); _EQ014 = !G711_in6 & _LC6_B1 # G711_in5 & G711_in6 & _LC1_B12; -- Node name is '|lpm_clshift:lpm_2|sbit3_7' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC7_B3', type is buried _LC7_B3 = LCELL( _EQ015); _EQ015 = !G711_in6 & _LC2_B2 # !G711_in4 & G711_in5 & G711_in6; -- Node name is '|lpm_clshift:lpm_2|:353' from file "lpm_clshift.tdf" line 101, column 9 -- Equation name is '_LC4_B1', type is buried _LC4_B1 = LCELL( _EQ016); _EQ016 = !G711_in5 & !G711_in6 & _LC1_B12 # G711_in5 & !G711_in6 & _LC7_B1; -- Node name is '|lpm_clshift:lpm_2|:354' from file "lpm_clshift.tdf" line 101, column 9 -- Equation name is '_LC3_B2', type is buried _LC3_B2 = LCELL( _EQ017); _EQ017 = !G711_in6 & _LC7_B2; -- Node name is '|lpm_clshift:lpm_2|:355' from file "lpm_clshift.tdf" line 101, column 9 -- Equation name is '_LC5_B3', type is buried _LC5_B3 = LCELL( _EQ018); _EQ018 = G711_in5 & !G711_in6 & _LC1_B12; -- Node name is '|lpm_clshift:lpm_2|:356' from file "lpm_clshift.tdf" line 101, column 9 -- Equation name is '_LC1_B9', type is buried _LC1_B9 = LCELL( _EQ019); _EQ019 = !G711_in4 & G711_in5 & !G711_in6; -- Node name is '|lpm_clshift:lpm_2|:396' from file "lpm_clshift.tdf" line 106, column 28 -- Equation name is '_LC6_B2', type is buried _LC6_B2 = LCELL( _EQ020); _EQ020 = G711_in6 & _LC4_B2; -- Node name is '|lpm_clshift:lpm_2|:398' from file "lpm_clshift.tdf" line 106, column 28 -- Equation name is '_LC8_B1', type is buried _LC8_B1 = LCELL( _EQ021); _EQ021 = G711_in6 & _LC6_B1; -- Node name is '|shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit1_1' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC8_A4', type is buried _LC8_A4 = LCELL( _EQ022); _EQ022 = !_LC2_A11 & PCM_in1 # _LC2_A11 & PCM_in2; -- Node name is '|shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit1_2' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC8_A5', type is buried !_LC8_A5 = _LC8_A5~NOT; _LC8_A5~NOT = LCELL( _EQ023); _EQ023 = !PCM_in2 & !PCM_in3 # _LC2_A11 & !PCM_in3 # !_LC2_A11 & !PCM_in2; -- Node name is '|shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit1_3' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC7_A4', type is buried _LC7_A4 = LCELL( _EQ024); _EQ024 = !_LC2_A11 & PCM_in3 # _LC2_A11 & PCM_in4; -- Node name is '|shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit1_4' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC7_A5', type is buried !_LC7_A5 = _LC7_A5~NOT; _LC7_A5~NOT = LCELL( _EQ025); _EQ025 = !PCM_in4 & !PCM_in5 # _LC2_A11 & !PCM_in5 # !_LC2_A11 & !PCM_in4; -- Node name is '|shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit1_5' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC8_A12', type is buried _LC8_A12 = LCELL( _EQ026); _EQ026 = !_LC2_A11 & PCM_in5 # _LC2_A11 & PCM_in6; -- Node name is '|shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit1_6' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC1_A8', type is buried !_LC1_A8 = _LC1_A8~NOT; _LC1_A8~NOT = LCELL( _EQ027); _EQ027 = !_LC2_A11 & !PCM_in6 # _LC2_A11 & !PCM_in7 # !PCM_in6 & !PCM_in7; -- Node name is '|shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit1_7' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC1_A9', type is buried _LC1_A9 = LCELL( _EQ028); _EQ028 = !_LC2_A11 & PCM_in7 # _LC2_A11 & PCM_in8; -- Node name is '|shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit1_8' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC1_A10', type is buried !_LC1_A10 = _LC1_A10~NOT; _LC1_A10~NOT = LCELL( _EQ029); _EQ029 = !_LC2_A11 & !PCM_in8 # _LC2_A11 & !PCM_in9 # !PCM_in8 & !PCM_in9; -- Node name is '|shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit1_9' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC1_A11', type is buried _LC1_A11 = LCELL( _EQ030); _EQ030 = !_LC2_A11 & PCM_in9 # PCM_in10 & PCM_in11; -- Node name is '|shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit2_0' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC2_A5', type is buried !_LC2_A5 = _LC2_A5~NOT; _LC2_A5~NOT = LCELL( _EQ031); _EQ031 = !_LC2_A11 & !_LC8_A5 # !_LC1_A6 & !_LC2_A11 # _LC1_A6 & !_LC8_A5 # !_LC8_A5 & !PCM_in1 # !_LC1_A6 & !PCM_in1; -- Node name is '|shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit2_1' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC3_A4', type is buried _LC3_A4 = LCELL( _EQ032); _EQ032 = !_LC1_A6 & _LC8_A4 # _LC1_A6 & _LC7_A4; -- Node name is '|shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit2_2' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC3_A5', type is buried !_LC3_A5 = _LC3_A5~NOT; _LC3_A5~NOT = LCELL( _EQ033); _EQ033 = !_LC7_A5 & !_LC8_A5 # _LC1_A6 & !_LC7_A5 # !_LC1_A6 & !_LC8_A5; -- Node name is '|shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit2_3' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC4_A4', type is buried _LC4_A4 = LCELL( _EQ034); _EQ034 = !_LC1_A6 & _LC7_A4 # _LC1_A6 & _LC8_A12; -- Node name is '|shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit2_4' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC4_A5', type is buried !_LC4_A5 = _LC4_A5~NOT; _LC4_A5~NOT = LCELL( _EQ035); _EQ035 = !_LC1_A8 & !_LC7_A5 # _LC1_A6 & !_LC1_A8 # !_LC1_A6 & !_LC7_A5; -- Node name is '|shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit2_5' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC5_A4', type is buried _LC5_A4 = LCELL( _EQ036); _EQ036 = !_LC1_A6 & _LC8_A12 # _LC1_A6 & _LC1_A9; -- Node name is '|shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit2_6' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC5_A5', type is buried !_LC5_A5 = _LC5_A5~NOT; _LC5_A5~NOT = LCELL( _EQ037); _EQ037 = !_LC1_A8 & !_LC1_A10 # _LC1_A6 & !_LC1_A10 # !_LC1_A6 & !_LC1_A8; -- Node name is '|shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit2_7' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC6_A4', type is buried _LC6_A4 = LCELL( _EQ038); _EQ038 = _LC1_A6 & _LC1_A11 # !_LC1_A6 & _LC1_A9; -- Node name is '|shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit3_0' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC6_A5', type is buried !_LC6_A5 = _LC6_A5~NOT; _LC6_A5~NOT = LCELL( _EQ039); _EQ039 = !_LC4_A5 & _LC7_A7 # !_LC2_A5 & !_LC4_A5 # !_LC2_A5 & !_LC7_A7; -- Node name is '|shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit3_1' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC2_A4', type is buried _LC2_A4 = LCELL( _EQ040); _EQ040 = _LC5_A4 & _LC7_A7 # _LC3_A4 & !_LC7_A7; -- Node name is '|shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit3_2' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC1_A5', type is buried !_LC1_A5 = _LC1_A5~NOT; _LC1_A5~NOT = LCELL( _EQ041); _EQ041 = !_LC3_A5 & !_LC5_A5 # !_LC3_A5 & !_LC7_A7 # !_LC5_A5 & _LC7_A7; -- Node name is '|shift:lpm_1|lpm_clshift:lpm_clshift_component|sbit3_3' from file "lpm_clshift.tdf" line 106, column 10 -- Equation name is '_LC1_A4', type is buried _LC1_A4 = LCELL( _EQ042); _EQ042 = _LC4_A4 & !_LC7_A7 # _LC6_A4 & _LC7_A7; -- Node name is '~437~1' -- Equation name is '~437~1', location is LC3_A11, type is buried. -- synthesized logic cell _LC3_A11 = LCELL( _EQ043); _EQ043 = PCM_in6 & !PCM_in7 # PCM_in8; -- Node name is ':437' -- Equation name is '_LC2_A11', type is buried !_LC2_A11 = _LC2_A11~NOT; _LC2_A11~NOT = LCELL( _EQ044); _EQ044 = _LC3_A11 & !PCM_in9 & !PCM_in11 # PCM_in10 & !PCM_in11; -- Node name is ':455' -- Equation name is '_LC4_A6', type is buried _LC4_A6 = LCELL( _EQ045); _EQ045 = PCM_in7 & !PCM_in8 & !PCM_in9 # PCM_in6 & !PCM_in8 & !PCM_in9; -- Node name is ':456' -- Equation name is '_LC1_A6', type is buried _LC1_A6 = LCELL( _EQ046); _EQ046 = PCM_in11 # PCM_in10 # _LC4_A6; -- Node name is ':469' -- Equation name is '_LC7_A7', type is buried !_LC7_A7 = _LC7_A7~NOT; _LC7_A7~NOT = LCELL( _EQ047); _EQ047 = !PCM_in8 & !PCM_in9 & !PCM_in10 & !PCM_in11; -- Node name is ':514' -- Equation name is '_LC2_A6', type is buried _LC2_A6 = LCELL( _EQ048); _EQ048 = PCM_in7 # PCM_in6 # _LC7_A7; -- Node name is ':522' -- Equation name is '_LC3_A6', type is buried !_LC3_A6 = _LC3_A6~NOT; _LC3_A6~NOT = LCELL( _EQ049); _EQ049 = _LC2_A6 & !_LC2_A11 # !_LC2_A6 & !PCM_in5 # !_LC2_A11 & !PCM_in5; -- Node name is ':783' -- Equation name is '_LC2_B8', type is buried !_LC2_B8 = _LC2_B8~NOT; _LC2_B8~NOT = LCELL( _EQ050); _EQ050 = !G711_in5 & G711_in6; Project Information c:\study\vhdl\codecs\g711.3\g711.rpt ** COMPILATION SETTINGS & TIMES ** Processing Menu Commands ------------------------ Design Doctor = off Logic Synthesis: Synthesis Type Used = Multi-Level Default Synthesis Style = NORMAL Logic option settings in 'NORMAL' style for 'FLEX10K' family CARRY_CHAIN = ignore CARRY_CHAIN_LENGTH = 32 CASCADE_CHAIN = ignore CASCADE_CHAIN_LENGTH = 2 DECOMPOSE_GATES = on DUPLICATE_LOGIC_EXTRACTION = on MINIMIZATION = full MULTI_LEVEL_FACTORING = on NOT_GATE_PUSH_BACK = on REDUCE_LOGIC = on REFACTORIZATION = on REGISTER_OPTIMIZATION = on RESYNTHESIZE_NETWORK = on SLOW_SLEW_RATE = off SUBFACTOR_EXTRACTION = on IGNORE_SOFT_BUFFERS = on USE_LPM_FOR_AHDL_OPERATORS = off Other logic synthesis settings: Automatic Global Clock = on Automatic Global Clear = on Automatic Global Preset = on Automatic Global Output Enable = on Automatic Fast I/O = off Automatic Register Packing = off Automatic Open-Drain Pins = on Automatic Implement in EAB = off Optimize = 5 Default Timing Specifications: None Cut All Bidir Feedback Timing Paths = on Cut All Clear & Preset Timing Paths = on Ignore Timing Assignments = off Functional SNF Extractor = off Linked SNF Extractor = off Timing SNF Extractor = on Optimize Timing SNF = off Generate AHDL TDO File = off Fitter Settings = NORMAL Smart Recompile = off Total Recompile = off Interfaces Menu Commands ------------------------ EDIF Netlist Writer = off Verilog Netlist Writer = off VHDL Netlist Writer = off Compilation Times ----------------- Compiler Netlist Extractor 00:00:01 Database Builder 00:00:00 Logic Synthesizer 00:00:01 Partitioner 00:00:00 Fitter 00:00:01 Timing SNF Extractor 00:00:00 Assembler 00:00:01 -------------------------- -------- Total Time 00:00:04 Memory Allocated ----------------- Peak memory allocated during compilation = 9,553K @ 1.1.1.1 log @no message @ text @@