The Wishbone Monitor Cotroller Central Core is 100% Wishbone compatible with the WishboneTK extensions. It incorporates 3 Wishbone interfaces. One salve interface for register accesses another slave interface for pixel memory accesses and one master interface for the pixel memory. Arbitation between the core and the external master accessing the pixel memory handled by the core internally.
| Description | Specification | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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| General Description | Monitor controller central core. | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Supported cycles | Slave read/write Slave block read/write Slave rmw Master read/write Master block read/write Master rmw | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Data port size | Configurable on slave side, 16-bits on the master side | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Data port granularity | 8-bit | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Data port maximum operand size | Bus size | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Data transfer ordering | Little endien | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Data transfer sequencing | n/a | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Supported signal list and cross reference to equivalent Wishbone signals |
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| Parameter name | Description |
|---|---|
| v_dat_width | Pixel memory data width |
| v_adr_width | Pixel memory address width |
| cpu_dat_width | CPU data width |
| cpu_adr_width | Pixel memory access interface address width |
| reg_adr_width | Register access interface address width |
| fifo_size | Size of the internal FIFO buffers in v_dat_width bits |
| Signal name | Description |
|---|---|
| Signals to connect to the pixel memory master | |
| VMEM_CYC_I | Wishbone cycle signal. High value frames blocks of access |
| VMEM_STB_I | Wishbone strobe signal. High value indicates cycle to this particular device |
| VMEM_WE_I | Wishbone write enable signal. High indicates data flowing from master to slave |
| VMEM_ACK_O | Wishbone acknowledge signal. High indicates that slave finished operation sucessfully |
| VMEM_ACK_OI | WhisboneTK acknowledge chain input signal |
| VMEM_ADR_I(cpu_adr_width-1..0) | Wishbone address bus signals |
| VMEM_SEL_I(cpu_dat_width/8-1..0) | Wishbone byte-selection signals |
| VMEM_DAT_I(cpu_dat_width-1..0) | Wishbone data bus input (to slave direction) signals |
| VMEM_DAT_O(cpu_dat_width-1..0) | Wishbone data bus output (to master direction) signals |
| VMEM_DAT_OI(cpu_dat_width-1..0) | WhisboneTK data bus chain input signal |
| Signals to connect to the register master | |
| REG_CYC_I | Wishbone cycle signal. High value frames blocks of access |
| REG_STB_I | Wishbone strobe signal. High value indicates cycle to this particular device |
| REG_WE_I | Wishbone write enable signal. High indicates data flowing from master to slave |
| REG_ACK_O | Wishbone acknowledge signal. High indicates that slave finished operation sucessfully |
| REG_ACK_OI | WhisboneTK acknowledge chain input signal |
| REG_ADR_I(reg_adr_width-1..0) | Wishbone address bus signals |
| REG_SEL_I(cpu_dat_width/8-1..0) | Wishbone byte-selection signals |
| REG_DAT_I(cpu_dat_width-1..0) | Wishbone data bus input (to slave direction) signals |
| REG_DAT_O(cpu_dat_width-1..0) | Wishbone data bus output (to master direction) signals |
| REG_DAT_OI(cpu_dat_width-1..0) | WhisboneTK data bus chain input signal |
| Signals to connect to the pixel memory | |
| V_CYC_O | Wishbone cycle signal. High value frames blocks of access |
| V_STB_O | Wishbone strobe signal. High value indicates cycle to this particular device |
| V_WE_O | Wishbone write enable signal. High indicates data flowing from master to slave |
| V_ACK_I | Wishbone acknowledge signal. High indicates that slave finished operation sucessfully |
| V_ADR_O(m_addr_width-2..0) | Wishbone address bus signals |
| V_SEL_O(s_bus_width/8-1..0) | Wishbone byte-selection signals |
| V_DAT_I(s_bus_width-1..0) | Wishbone data bus input (to slave direction) signals |
| V_DAT_O(s_bus_width-1..0) | Wishbone data bus output (to master direction) signals |
| Non Wishbone signals | |
| H_SYNC | Horizontal sync pulse. Active level programmable. |
| H_BLANK | Horizontal blank pulse. Active level programmable. |
| V_SYNC | Vertical sync pulse. Active level programmable. |
| V_BLANK | Vertical blank pulse. Active level programmable. |
| H_TC | Horizontal terminal count. Active high signal, active for one clock cycle/line |
| V_TC | Vertical terminal count. Active high signal, active for one clock cycle/refresh |
| BLANK | Blank signal. Active high signal. |
| VIDEO_OUT(7 downto 0) | 8-bit video output. If bit-depth is less than 8, value is right alligned and padded with 0s. |
The core has several programmable registers which control its behaviour. All registers can be written and checked. All registers reset to 0. It is recomended that the enable bit turned off prior any write to any of the registers and than enable bit turned off after all registers are programmed to their new values. Registers are shown in 8-bit layout however the actual grouping of registers into access units depending on the bus-width of the CPU interface. Address-decoding is allways little-endien.
| Offset | Bit number | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
| 0 | V_MEM_END | Last location in the memory being part of the frame buffer. Counted in v_dat_width units. | |||||||
| 1 | |||||||||
| 2 | |||||||||
| 3 | |||||||||
| 4 | V_MEM_START | First location in the memory being part of the frame buffer. Counted in v_dat_width units. | |||||||
| 5 | |||||||||
| 6 | |||||||||
| 7 | |||||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
| 8 | reserved | ||||||||
| 9 | |||||||||
| 10 | |||||||||
| 11 | |||||||||
| 12 | |||||||||
| 13 | |||||||||
| 14 | |||||||||
| 15 | |||||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
| 16 | FIFO_TRESHOLD | Number of words in the internal pixel FIFO after pixel memory access priority changes. | |||||||
| 17 | res. | MSS | res. | BPP | MSS: Multi-scan-select. If 0 multi-scan feature is disabled. BSS: Bits per pixel. 00 - 1 bpp, 01 - 2 bpp, 10 - 4 bpp, 11 - 8 bpp | ||||
| 18 | HBS | Horizontal blank start in 8 pixels. (Horizontal resolution) | |||||||
| 19 | HSS | Horizontal sync pulse start in 8 pixels. | |||||||
| 20 | HSE | Horizontal sync pulse end in 8 pixels. | |||||||
| 21 | HTOTAL | Horizontal line total length in 8 pixels. | |||||||
| 22 | VBS | Vertical blank start in 8 lines. (Vertical resolution) | |||||||
| 23 | VSS | Vertical sync pulse start in 8 lines. | |||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
| 24 | VSE | Vertical sync pulse end in 8 lines. | |||||||
| 25 | VTOTAL | Vertical total screen size in 8 lines. | |||||||
| 26 | PSS | Pixel pre-scaler: Pixel-clock := System-clock/(PSS+1). | |||||||
| 27 | EN | res. | VBP | HBP | VSP | HSP | EN: 1 - normal operation, 0 - core is in reset state HSP: 0 - positive h sync, 1 - negative h sync VSP: 0 - positive v sync, 1 - negative v sync HBP: 0 - positive h blank, 1 - negative h blank VBP: 0 - positive v blank, 1 - negative v blank | ||
| 28 | reserved | ||||||||
| 29 | |||||||||
| 30 | |||||||||
| 31 | |||||||||
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
Of course the FPGA cannot provide the correct signal levels not to mention the analog output required by VGA monitors. This statement means that all the necessary sync signals can be generated.
On VGA monitors low resolution modes (320x200, 320x240) are generated with this feature. Each video memory line scanned twice, so the physical screen will contain 400/480 scan-lines.
The use of FIFO buffer allows long bursts from the CPU without being interrupted by the pixel generation engine. It also somewhat relaxes memory speed requirements as FIFO-fill cycles can continue through blanking periods.
This device is designed to be simple and easy to use. It's not about using many megs of frame-buffer. The optimal size of the frame-buffer would be around 64kWords. Such a size of memory can most easily be constructed from SRAM chips. They are also faster and easier to interface to than DRAM let alone SDRAM devices. An external Wishbone bus interface should be used to interface the core to the pixel memory so any memory type that has such an interface can be used. For SRAM devices the WisboneTK Asyncronous slave interface in a practical choice.
Depends of course on technology but this is the minimum to support reasonable resolutions with usable refresh-rates.