WisboneTK

Asyncronous master interface

Description

Asyncronous master interface is a simple parametrized bus converter. It acts as a slave device for an asyncron CPU-like master device and converts cycles to wishbone compatible bus access cycles. That type of bus interface is very common between slow to middle speed CPUs and MCUs available on the market. With this core it is possible to use those Wishbone peripherials from those device. The core is 100% Wishbone compatible with the WishboneTK extensions. The address and data bus-width can be configured through compile-time parameters. The speed of the asyncronous bus is controled by the wait signal.

Wishbone datasheet

DescriptionSpecification
General Description Asyncronous master interface
Supported cycles Master read/write
Master block read/write
Master rmw
Data port size variable
Data port granularity 8-bit
Data port maximum operand size same as data port size
Data transfer ordering n/a
Data transfer sequencing n/a
Supported signal list and cross reference to equivalent Wishbone signals
Signal nameWishbone equiv.
S_CLK_I CLK_I
S_RST_I RST_I
S_CYC_O CYC_O
S_STB_O STB_O
S_WE_O WE_O
S_ACK_I ACK_I
S_RTY_I RTY_I
S_ERR_I ERR_I
S_SEL_O(..) SEL_O()
S_ADR_O(..) ADR_O()
S_DAT_I(..) DAT_I()
S_DAT_O(..) DAT_O()

Parameter description

Parameter nameDescription
widthData bus width
addr_widthAddress bus width

Signal description

Signal nameDescription
S_CYC_O Wishbone cycle signal. High value frames blocks of access
S_STB_O Wishbone strobe signal. High value indicates cycle to this particular device
S_WE_O Wishbone write enable signal. High indicates data flowing from master to slave
S_ACK_I Wishbone acknowledge signal. High indicates that slave finished operation sucessfully
S_RTY_I Wishbone retry signal. High indicates that slave requests retry of the last cycle in the block.
S_ERR_I Wishbone error signal. High indicates that slave cannot complete the last cycle in the block.
S_ADR_O(addr_width-2..0) Wishbone address bus signals
S_SEL_O(width/8-1..0) Wishbone byte-selection signals
S_DAT_I(width-1..0) Wishbone data bus input (to slave direction) signals
S_DAT_O(width-1..0) Wishbone data bus output (to master direction) signals
Aysncronous interfce signals
A_DATA(width-1..0)Bidirectional data bus signals
A_ADDR(addr_width-1..0)Address bus output signals
A_RDNActive low read signal
A_WRNActive low write signal
A_CENActive low chip-select signal
A_BYEN(addr_width/8-1..0)Active-low byte-enable signals
A_WAITNActive low wait signal

Author & Maintainer

Andras Tantos