WisboneTK

WishboneTK two-way arbiter

Description

WishboneTK two-way arbiter connectrs two master devices to a set of shared slave devies. From the master devices point of view the shared peripherials will look like a single slave inserted into their local slave's chain. From the shared slaves point of view the arbiter will act as a master device on behalf of the two real masters. The core is 100% Wishbone compatible with the WishboneTK extensions. Address select and data buses should be multiplexed to the common interface externaly but handshake signals are handled by the core. Multiplexer control signals are also provided. The core is asyncronous to support zero-wait-state operation on the shared bus. Thus the CLK_I signal, required for most Wishbone devies is not used.

Wishbone datasheet

DescriptionSpecification
General Description Two-way arbiter.
Supported cycles Slave read/write
Slave block read/write
Slave rmw
Master read/write
Master block read/write
Master rmw
Data port size n/a
Data port granularity n/a
Data port maximum operand size n/a
Data transfer ordering n/a
Data transfer sequencing n/a
Supported signal list and cross reference to equivalent Wishbone signals
Signal nameWishbone equiv.
RST_I RST_I
Signals to connect to master A
A_CYC_I CYC_I
A_STB_I STB_I
A_WE_I WE_I
A_ACK_O ACK_O
A_RTY_O RTY_O
A_ERR_O ERR_O
Signals to connect to master B
B_CYC_I CYC_I
B_STB_I STB_I
B_WE_I WE_I
B_ACK_O ACK_O
B_RTY_O RTY_O
B_ERR_O ERR_O
Signals to connect to shared slaves
S_CYC_O CYC_O
S_STB_O STB_O
S_WE_O WE_O
S_ACK_I ACK_I
S_RTY_I RTY_I
S_ERR_I ERR_I

Signal description

Signal nameDescription
Signals to connect to master A
A_RST_I Wishbone reset signal
A_CYC_I Wishbone cycle signal. High value frames blocks of access
A_STB_I Wishbone strobe signal. High value indicates cycle to this particular device
A_WE_I Wishbone write enable signal. High indicates data flowing from master to slave
A_ACK_O Wishbone acknowledge signal. High indicates that slave finished operation sucessfully
A_ACK_OI WhisboneTK acknowledge chain input signal
A_RTY_O Wishbone retry signal. High indicates that slave requests retry of the last cycle in the block.
A_RTY_OI WhisboneTK retry chain input signal
A_ERR_O Wishbone error signal. High indicates that slave cannot complete the last cycle in the block.
A_ERR_OI WhisboneTK error chain input signal
Signals to connect to master B
B_RST_I Wishbone reset signal
B_CYC_I Wishbone cycle signal. High value frames blocks of access
B_STB_I Wishbone strobe signal. High value indicates cycle to this particular device
B_WE_I Wishbone write enable signal. High indicates data flowing from master to slave
B_ACK_O Wishbone acknowledge signal. High indicates that slave finished operation sucessfully
B_ACK_OI WhisboneTK acknowledge chain input signal
B_RTY_O Wishbone retry signal. High indicates that slave requests retry of the last cycle in the block.
B_RTY_OI WhisboneTK retry chain input signal
B_ERR_O Wishbone error signal. High indicates that slave cannot complete the last cycle in the block.
B_ERR_OI WhisboneTK error chain input signal
Signals to connect to shared slaves
S_CYC_O Wishbone cycle signal. High value frames blocks of access
S_STB_O Wishbone strobe signal. High value indicates cycle to this particular device
S_WE_O Wishbone write enable signal. High indicates data flowing from master to slave
S_ACK_I Wishbone acknowledge signal. High indicates that slave finished operation sucessfully
S_RTY_I Wishbone retry signal. High indicates that slave requests retry of the last cycle in the block.
S_ERR_I Wishbone error signal. High indicates that slave cannot complete the last cycle in the block.

Author & Maintainer

Andras Tantos