**Project
Name: Viterbi Decoder**

**Introduction**

Viterbi Algorithm has been a legendary decoding
algorithm for Convolutional Codes. It was found by Andrew J. Viterbi
which was published on his paper "Error Bounds for Convolutional
Codes and an Asymptotically Optimum Decoding Algorithm," in *IEEE
Transactions on Information Theory*, Volume IT-13, April 1967.
Research and development then increasing to find more better and more
eficient code generator for the Convolutional Codes and the
architectural implementation of the Viterbi Algorithm.

Viterbi Algorithm is well used to find a maximally-likelihood decoded bits from a convolutional coded transmitted bits which transmission channel is interferenced by heavy noise such as Additive White Noise Gaussian (AWGN). Enough redundancies are added to combat the impairment of the transmission channel. As a result, Viterbi Algorithm could get an amazing low decoded Bit Error Rate (BER) compared to uncoded transmitted bits, showed by its BER to Eb/No graphical property. This performance could be parameterized by the Constraint Length (K) and Code Rate (R) of the Convolutional Encoder. And yes, we have trade offs around speed, area, and power while trying to implement the Viterbi Algorithm in a real hardware (full/semi custom VLSI).

Very short explanation on Viterbi Algorithm written by Zalfany could be found here. Find more on the Link Section

**Current Status**

VDK3R1/2 is available on CVS repository. [Very simple, easy to debug, and could be used for initial study of Viterbi Decoder, I hope :-)] (May 2000).

Finished working on functional & design specifications of VDK7R1/2. Behavioural simulation using is OK. No source is available, as we decide to skip this and moved to decoder with K=9.

First release for VDK9R1/2, still much work, fix and "flames" needed (February 2001). The source is synthesizable, except for the register (memory) part.

Branch Metric Generator and Add Compare Select Unit of VDK9R1/2 has been implemented on Xilinx Virtex FPGA XCV 300.

**Specifications**

- Encoding Rate (R) : 1/2
- Constraint Length (K) : 3
- Generator Polynomials : 7
_{8}and 5_{8} - Big Endian Encoded Input
- Hard Decision

VDK7R1/2

- Stopped, moved on to the next specs.

- Encoding Rate (R) : 1/2
- Constraint Length (K) : 9
- Generator Polynomials : 753
_{8}and 561_{8} - Big Endian Encoded Input
- 3 bit quantized Soft Decision

__N__ext Steps

__See__each specs page for detailed TODO List.- Create Link Sections [where was my bookmarks ? :-)]
- Punctured Code (?)
- Documentation.

**Documentation**

**Software & Tools**

**Author & Maintainer:**

**Mailing list:**