Project Name: Serial UART



Serial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing the Serial UART core is the fact, that asynchronous serial communication is very common that almost every machine understands it.Also, for OCRP-1, we needed a way of communication with a host computer, to make it available over the net.


Synthesized with Xilinx Foundation 2.1i (Synopsys Express FPGA compiler, Xilinx P&R tools) for :

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