------------------------------------------------------------------------------ -- Title : ROBO_ARM -- Project : ROBOTIC ARM CONTROLLER ------------------------------------------------------------------------------- -- File : robo_arm.vhd -- Author : R.SATHISH KUMAR -- Created : 25-4-2001 -- Last update : ------------------------------------------------------------------------------- -- Description: --This vhdl module is a TOP LEVEL DESIGN OF ROBOTIC ARM CONTROLLER --Possible control of two step modes(full,half) & two direction(clockwise & anticlockwise) --It is a strutural description contains stepper_f ,stepper_h,sel_mux as components --------------------------------------------------------- library IEEE; use IEEE.std_logic_1164.all; use work.std_arith.all; entity robo_arm is port(CLK : in STD_LOGIC; DIR_SEL : in STD_LOGIC; --direction select STOP :in STD_LOGIC; --stop STEP_SEL:in STD_LOGIC; --step action select(full\half) ARM_IN:out STD_LOGIC_VECTOR(3 downto 0)); end robo_arm; architecture TOP of robo_arm is component stepper_f port(CLK : in STD_LOGIC; DIR_SEL : in STD_LOGIC; STEP_SEL:in STD_LOGIC; STOP :in STD_LOGIC; DATA_OUT : out STD_LOGIC_VECTOR(3 downto 0)); end component; component stepper_h port(CLK : in STD_LOGIC; DIR_SEL : in STD_LOGIC; STEP_SEL:in STD_LOGIC; STOP :in STD_LOGIC; DATA_OUT_H : out std_logic_vector(3 downto 0)); end component; component sel_mux port( DATA_OUT : in STD_LOGIC_VECTOR(3 downto 0); DATA_OUT_H : in STD_LOGIC_VECTOR(3 downto 0); STEP_SEL: in STD_LOGIC; ARM:out STD_LOGIC_VECTOR(3 downto 0)); end component; signal data_out: std_logic_vector(3 downto 0); signal data_out_h : std_logic_vector(3 downto 0); signal arm : std_logic_vector(3 downto 0); begin T1: stepper_f port map (CLK ,DIR_SEL,STEP_SEL,STOP,DATA_OUT); T2: stepper_h port map (CLK ,DIR_SEL,STEP_SEL,STOP,DATA_OUT_H); T3: sel_mux port map ( DATA_OUT,DATA_OUT_H,STEP_SEL,ARM); ARM_IN <= ARM; end TOP;