Description
OpenRISC 1000 is an architecture of a family of open source, synthesizeable RISC microprocessor cores. It is a 32-bit load and store RISC architecture designed with emphasis on speed, compact instruction set and scalability. OpenRISC 1000 targets wide range of embedded environments.
Performance features include fully 32-bit architecture, powerful virtual memory support, cache coherency, optional SMP and SMT support and optional static scheduling information. Architecture defines several features for embedded environments. Most notable are mixed 32-bit and 16-bit instruction word sizes, instruction set optimized for embedded environments, configurable number of general purpose registers, configurable cache and TLB sizes, dynamic power management support and space for user provided instructions.
OpenRISC 1000 architecture is a predecessor of more powerful and feature richful next generation OpenRISC architectures.
Implementions of the OpenRISC 1000 architecture will be available in full source at this web site and will be supported with GNU software development tools, with a port of open source Linux(tm) operating system, with a port of open source Cygnus eCos(tm) real time operating system and with a architectural and implementation simulators. Most implementations will be designed modular and vendor independent. They will be able to interface with other open source cores available from this web site. Examples of such additional cores are SDRAM and PCI controllers.
Implementations of the architecture vary in performance and complexness. Some are targeting highly embedded applications with low gate count, low performance ( < 1 Dhrystone MIPS / MHz) and low power requirements. Others target high performance embedded applications with performance of 2 and more Dhrystone MIPS / MHz.
First OpenRISC 1000 implementation will be able to compare with ARM7+ core.
Opencores.org encourages companies to design and market their own implementations of the OpenRISC 1000 architecture.
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