OpenRISC 1000 Project: Roadmap

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Introduction

The aim of this project is to define the basic OpenRISC 1000 architecture and to add improvements and extensions in the future.

OpenRISC 1000 is architecture for a family of free, open source RISC processor cores. As an architecture, OpenRISC 1000 allows for a spectrum of chip and system implementations at a variety of price/performance points for a range of applications. It is a 32/64-bit load and store RISC architecture designed with emphasis on performance, simplicity, low power requirements, scalability and versatility. OpenRISC 1000 architecture targets medium and high performance networking, embedded, automotive and portable computer environments.

Performance features include fully 32/64-bit architecture, vector, DSP and floating-point instructions, powerful virtual memory support, cache coherency, optional SMP and SMT support and support for fast context switching. Architecture defines several features for networking and embedded computer environments. Most notable are several instruction extensions, configurable number of general-purpose registers, configurable cache and TLB sizes, dynamic power management support and space for user provided instructions. OpenRISC 1000 architecture is a predecessor of more powerful and richful next generation OpenRISC architectures.

Features

OpenRISC 1000 architecture includes the following principal features:

Status

If you would like to help with the development, please contact the developers.

Documentation

Latest OpenRISC architecture manual is available from the OpenCores CVS under module name or1k/docs:

Wish List (TODO List)

This is a what we want to do/have in the future and right now nobody is working on this. If you want to help, send an email to the mailing list.

If you have a suggestion for new Wish List entry, feel free to send it to the mailing list so that is added to the list and somebody may start working on it.

Past Contributors

These are the people currently not working on the OpenRISC, but have contributed in the past:

Current Developer(s)

The team working on the OpenRISC architecture:

Mailing list / Discussion Forum

To participate in the development or simply to discuss OR1K architecture issues, go to the openrisc mailing list. To subscribe to the list, follow mailing list subscribe instructions.

Page Maintainer

This web page is maintained by Damjan Lampret.