OPENCORES Application Board 1 (OAB1)
you know, we have lots of free IP cores here, and we’ll have more coming soon.
We have to use these cores otherwise they are invaluable. For this reason the
idea of designing serials and open design boards are going to be available for
any designers around the world.
project is intended to:
design schematic can deal with analog signal and transport through Ethernet.
implementation CPU core and Ethernet core to one FPGA chip
program the necessary operation system and application software to achieve
build the prototype board.
do the test for all functions.
project can be divided into two parts. The board design and the cores design.
Anyone can use free or commercial tools to design and implement this project
design flow can be done through four steps:
Diagram design: I hope we use word 97+ for easy modify and exchange.
entry: I will post schematic using PDF format. Anyone can also send me using
PDF, protel99se or Cadence format.
design: The final layout will use Allegro or Protel99se.
implementation: This is the final step in the design where the designer
should work himself to produce his board unless we get funding or donation
from PCB manufactory.
design flow can be done through five steps:
entry: Doesn’t matter the tools, we exchange only VHDL or Verilog codes.
I hope to use ModelSim or Active-HDL, but other tools also welcome.
I hope to use FPGA express, but other tools also welcome.
I hope to use Xilinx FPGA.
Download: Using onboard parallel cable.
is the Board block diagram
system is composed of 5 main blocks:
Upload Board block diagram version 0.1
Upload Board block diagram version 0.2
References tools and links