Project Name: Memory coresDescription
Check the memory cores site for more documentation atJamil Khatib site
Current Status:
- VHDL codes are stable and available on the CVS
- Some cores need test benchs
- we need more memory cores with different features
- we need more people to test the cores on real hardware
- You can download the memory codes from the CVS using the module name "memory_cores" and for new cores use module name "memory_cores2".
- Download Old memory cores (have some features that still not available in the new cores.
- Download memory cores files
- Download Dual port memory core Includes WISHBONE compatible interface core wrapper. The core uses single or dual clocks and other parametrizable cofigurations
- Download Single port memory core Includes WISHBONE compatible interface core wrapper. The core has several parametrizable cofigurations
- Download fifo buffer
- Note: it is recommended to download the whole module because files are dependent on each other
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