A Little Bit about Alliance

 

A.  Introduction

Alliance is a Computer Aided Design System for Very Large Scale Integrated Circuits (VLSI) design.  Alliance is a non-commercial software developed by Équipe Achitecture des Systèmes et Micro-Électronique, Laboratoire d'Informatique de Paris 6,Université Pierre et Marie Curie, France.  So, if you are interested in Alliance, you can get the software and more information at http://www-asim.lip6.fr .  We usually run this software under Linux Operating Systems (we use Red Hat Linux 6.2).

The ALLIANCE VHDL  is dedicated to digital synchronous circuits design, which is usually used for:

The ALLIANCE VHDL  is fully compatible with the IEEE VHDL standard Ref. 1076 (1987). That means that a VHDL description using the ALLIANCE subset can be simulated with any full-VHDL commercial compiler-simulator.

The VHDL description of a circuit is made of two separate parts: the external view and the internal view.

The external view defines the name of the circuit and its interface. The interface of a circuit is a list of ports. Each port is specified by its name, its mode, its type, its constraint for an array and, its kind.

The mode of a port depends only on the manner the port is used inside the circuit (in the internal view of the circuit). If the value of a port is to be read in the view of the description, the port must be declared with the mode IN. If the value of a port is to be written by the internal view, the port must be declared with the mode OUT. If both above conditions are satisfied the port must be declared with the mode INOUT.  Only structural and behavioural data flow are supported as internal view.

A circuit, a subcircuit, or a cell can have two different descriptions:

 

B.  Starting Using Alliance

We can start using Alliance by linking our workspace to the source of Alliance by typing :

                    source /home/cad/alliance/share/etc/alc_env.csh

here we assume that the Alliance is located in directory  /home/cad.

The next step is to set the environment of Alliance.  We usually use logic gates from sclib to develop a circuit.  So, we must set the environment by typing :
       

             setenv MBK_CATA_LIB .:/home/cad/alliance/archi/Linux/cells/sclib

We must know the symbolic name of gate that we use by seeing manual of sclib. To see manual of all about command we want to know, we can type

                                man name_of_command

After that, we can start our design by typing the source code in the text editor.  Our design can be from behavioural data flow description or logic circuit description.  We can write our comment like this :

                            /* our_comment */

If our design comes from behavioural data flow description, we save it with a  .vbe extension.  You can see examples of  behavioural D-Flip Flop design here.

If our design comes from logic circuit description, we save it with a   .c   extension. In order to write this file, we must follow the syntax below :

/*

   genlib.h is required for all genlib programs.

   it defines the set of functions we will use for schematic capture

*/

#include <genlib.h>

/*

  decoder.c is to become the `core' executable program. So we must

   define a main procedure main()

*/

main()
{
DEF_LOFIG("decoder");    /* decoder.c  is our file name */

/* define inputs and outputs of our system */

 

/*

   We start with the input terminals.

   Only signals and connectors can be vectorized.

*/

LOCON("x", IN, "x" );                 /* define input */
LOCON("res", IN, "res" );           /* define reset  input, if we need it */
LOCON("ck", IN, "ck" );             /* define clock input */

LOCON("z", INOUT, "z" );         /* define an output of a gate but acts as input of another gate */

 

/*

   Then,  the output terminals.

*/


LOCON("y[0:1]", OUT, "y[0:1]" );            /* define output consists of 2 bits*/

 

 

/*

   Then the supplies.

   They are inputs, but we like them better at the end of the

   description.

*/

LOCON("vdd", IN, "vdd" );         /* define vdd input */
LOCON("vss", IN, "vss" );             /* define vss input */

....

 

/* define all components that we use to develop our system */

 

LOINS("a2_y", "a1",  "x",  "m", "z", "vdd", "vss",0);

 

/*  a2_y is a simbolic name for 2 inputs and gate */

/*  a1 is our given name for this component where there must  be no same name in the same file */

/*  x and m is inputs of a1 */

/*  z is the output of a1  */

 

....

 

SAVE_LOFIG();

   exit(0);         /* necessary for the proper run of the Makefile */

} 

 

Here we can see the example .c file of 4-bit counter.

 

C.  Basic Alliance Tools

 

After that, we are now ready to actually design the chip and use the Alliance tools. The design flow for this little example is composed of 5 main steps:

First of all, we must make a structural file (.vst).  We can get structural view from our behavioural data flow description (.vbe)  file or from our .c file.  Here are the basic Alliance tools :

(i)  genlib

By using this tool, we can change our logic circuit description file (.c) into structural file (.vst) which more useful in next process. The command is :

                                                 genlib .c_file_name

(ii)  scmap

Our behavioural data flow description file (.vbe) can be changed into structural file (.vst) by using this tool. The command is :

                                                scmap .vbe_ file_name .vst_file_name

We can see the structural file (.vst) generated from the previous behavioural D-Flip Flop design here.

(iii)  asimut

This tool is usually used to simulate our design by giving some inputs.  We can see simulation results, which can be compared to our expected outputs.  We must create a test pattern file (.pat)  contains some inputs we will use in the simulation.  You can see the example of test pattern file here.  The command is :


 asimut .vst_file_name test_pattern_file_name simulation_results_file_name

(iv)  xsch

We can see logic circuit of our structural file by using this tools.

(v)  xpat

We can see timing diagrams of test pattern file (.pat) and our asimut result file (.pat) by using xpat tool.

(vi)  scr

Our structural file can be extracted into symbolic layout using scr.  The command is :
                                                    scr -sclib -p -r  file_name

This symbolic layout result (.ap) can be viewed by graal tool.

(vii)  s2r

Our symbolic layout can be changed into real layout by using s2r.  The command is :
                                                    s2r file_name 

This real layout (.cif) can be viewed by using dreal tool.

(viii)  lynx

Our real layout can be changed into new structural file (.al) by using lynx.  First, we must set the environmet by the command :

                                        setenv MBK_OUT_LO al

then we type the command :

                                         lynx  -v  .ap_file_name  output_file_name  -f

After this, we can do simulation post-layout on the old (.vst) and new (.al) structural file by using lvx.  The command is :

                                         lvx  vst  al  .vst_file_name  .al_file_name

Another way to compare the result is using asimut.  We can simulate the new structural file (.al) with the previous test pattern file using asimut.  But first, we must set the environment :

                                        setenv MBK_IN_LO al

then using asimut :

        asimut .al_file_name  testpattern_file_name  result_file_name          

After that we can compare the new simulation result with the previous simulation result.  We expect to get the same result.

 

To know more about Alliance and find tutorials, you can visit  http://www-asim.lip6.fr