A Instruction Summaries

The tables in this appendix summarize the assembly-language instruction set:

Table A-1 summarizes the main instruction set.
Table A-2 summarizes the floating-point instruction set.
Table A-3 summarizes the rounding and trapping modes supported by some floating-point instructions.

Most of the assembly-language instructions translate into single instructions in machine code.

The tables in this appendix show the format of each instruction in the main instruction set and the floating-point instruction set. The tables list the instruction names and the forms of operands that can be used with each instruction. The specifiers used in the tables to identify operands have the following meanings:

Operand Specifier Description

address A symbolic expression whose effective value is used as an address.

b_reg Base register. A register containing a base address to which is added an offset (or displacement) value to produce an effective address.

d_reg Destination register. A register that receives a value as a result of an operation.

d_reg/s_reg One register that is used as both a destination register and a source register.

label A label that identifies a location in a program.

no_operands No operands are specified.

offset An immediate value that is added to the contents of a base register to calculate an effective address.

palcode A value that determines the operation performed by a PAL instruction.

s_reg, s_reg1, s_reg2 Source registers. Registers whose contents are to be used in an operation.

val_expr An expression whose value is used as an absolute value.

val_immed An immediate value that is to be used in an operation.

jhint An address operand that provides a hint of where a jmp or jsr instruction will transfer control.

rhint An immediate operand that provides software with a hint about how a ret or jsr_coroutine instruction is used.

The tables in this appendix are segmented into groups of instructions that have the same operand options; the operands specified within a particular segment of the table apply to all of the instructions contained in that segment.

Table A-1: Main Instruction Set Summary

Instruction	Mnemonic	Operands
Load Address Load Byte Load Byte Unsigned Load Word Load Word Unsigned Load Sign Extended Longword Load Sign Extended Longword Locked Load Quadword Load Quadword Locked Load Quadword Unaligned Load Unaligned Word Load Unaligned Word Unsigned Load Unaligned Longword Load Unaligned Quadword	lda[Table Note 1] ldb ldbu ldw ldwu ldl[Table Note 1] ldl_l[Table Note 1] ldq[Table Note 1] ldq_l[Table Note 1] ldq_u[Table Note 1] uldw uldwu uldl uldq	`d_reg, address`
Store Byte Store Word Store Longword Store Longword Conditional Store Quadword Store Quadword Conditional Store Quadword Unaligned Store Unaligned Word Store Unaligned Longword Store Unaligned Quadword	stb stw stl[Table Note 1] stl_c[Table Note 1] stq[Table Note 1] stq_c[Table Note 1] stq_u[Table Note 1] ustw ustl ustq	`s_reg, address`

Load Address High Load Global Pointer	ldah[Table Note 1] ldgp	`d_reg,offset(b_reg)`
Load Immediate Longword Load Immediate Quadword	ldil ldiq	`d_reg,val_expr`
Branch if Equal to Zero Branch if Not Equal to Zero Branch if Less Than Zero Branch if Less Than or Equal to Zero Branch if Greater Than Zero Branch if Greater Than or Equal to Zero Branch if Low Bit is Clear Branch if Low Bit is Set	beq bne blt ble bgt bge blbc blbs	`s_reg,label`
Branch Branch to Subroutine	br bsr	`d_reg,label` or `label`
Jump Jump to Subroutine	jmp[Table Note 1] jsr[Table Note 1]	`d_reg,(s_reg),jhint` or `d_reg,(s_reg)` or `(s_reg),jhint` or `(s_reg)` or `d_reg,address` or `address`
Return from Subroutine Jump to Subroutine Return	ret jsr_coroutine[Table Note 1]	`d_reg,(s_reg),rhint` or `d_reg,(s_reg)` or `d_reg,rhint` or `d_reg` or `(s_reg),rhint` or `(s_reg)` or `rhint` or `no_operands`
Architecture Mask	amask	`s_reg,d_reg` or `val_immed,d_reg`
Clear Implementation Version	clr implver	`d_reg`
Absolute Value Longword Absolute Value Quadword Move Negate Longword (without overflow) Negate Longword (with overflow) Negate Quadword (without overflow) Negate Quadword (with overflow) Logical Complement (NOT) Sign-Extension Byte Sign-Extension Longword Sign-Extension Word	absl absq mov negl neglv negq negqv not sextb sextl sextw	`s_reg,d_reg` or `d_reg/s_reg` or `val_immed,d_reg`
Add Longword (without overflow) Add Longword (with overflow) Add Quadword (without overflow) Add Quadword (with overflow) Scaled Longword Add by 4 Scaled Quadword Add by 4 Scaled Longword Add by 8 Scaled Quadword Add by 8 Compare Signed Quadword Equal Compare Signed Quadword Less Than Compare Signed Quadword Less Than or Equal Compare Unsigned Quadword Less Than Compare Unsigned Quadword Less Than or Equal Multiply Longword (without overflow) Multiply Longword (with overflow) Multiply Quadword (without overflow) Multiply Quadword (with overflow) Subtract Longword (without overflow) Subtract Longword (with overflow) Subtract Quadword (without overflow) Subtract Quadword (with overflow) Scaled Longword Subtract by 4 Scaled Quadword Subtract by 4 Scaled Longword Subtract by 8	addl addlv addq addqv s4addl s4addq s8addl s8addq cmpeq cmplt cmple cmpult cmpule mull mullv mulq mulqv subl sublv subq subqv s4subl s4subq s8subl	`s_reg1,s_reg2,d_reg` or `d_reg/s_reg1,s_reg2` or `s_reg1,val_immed,d_reg` or `d_reg/s_reg1,val_immed`

Scaled Quadword Subtract by 8 Scaled Quadword Subtract by 8 Unsigned Quadword Multiply High Divide Longword Divide Longword Unsigned Divide Quadword Divide Quadword Unsigned Longword Remainder Longword Remainder Unsigned Quadword Remainder Quadword Remainder Unsigned Logical Product (AND) Logical Sum (OR) Logical Sum (OR) Logical Difference (XOR) Logical Product with Complement (ANDNOT) Logical Product with Complement (ANDNOT) Logical Sum with Complement (ORNOT) Logical Equivalence (XORNOT) Logical Equivalence (XORNOT) Move if Equal to Zero Move if Not Equal to Zero Move if Less Than Zero Move if Less Than or Equal to Zero Move if Greater Than Zero Move if Greater Than or Equal to Zero Move if Low Bit Clear Move if Low Bit Set Shift Left Logical Shift Right Logical Shift Right Arithmetic Compare Byte Extract Byte Low Extract Word Low Extract Longword Low Extract Quadword Low Extract Word High Extract Longword High Extract Quadword High Insert Byte Low Insert Word Low Insert Longword Low Insert Quadword Low	s8subq s8subq umulh divl divlu divq divqu reml remlu remq remqu and bis or xor bic andnot ornot eqv xornot cmoveq cmovne cmovlt cmovle cmovgt cmovge cmovlbc cmovlbs sll srl sra cmpbge extbl extwl extll extql extwh extlh extqh insbl inswl insll insql	`s_reg1,s_reg2,d_reg` or `d_reg/s_reg1,s_reg2` or `s_reg1,val_immed,d_reg` or `d_reg/s_reg1,val_immed`
Insert Word High Insert Word High Insert Longword High Insert Quadword High Mask Byte Low Mask Word Low Mask Longword Low Mask Quadword Low Mask Word High Mask Longword High Mask Quadword High Zero Bytes Zero Bytes NOT	inswh inswh inslh insqh mskbl mskwl mskll mskql mskwh msklh mskqh zap zapnot	`s_reg1,s_reg2,d_reg` or `d_reg/s_reg1,s_reg2` or `s_reg1,val_immed,d_reg` or `d_reg/s_reg1,val_immed`
Call Privileged Architecture Library	call_pal	`palcode`
Prefetch Data Prefetch Data, Modify Intent	fetch fetch_m	`offset(b_reg)`
Read Process Cycle Counter	rpcc	`d_reg`
No Operation Universal No Operation Trap Barrier Exception Barrier Memory Barrier Write Memory Barrier	nop unop trapb excb mb wmb	`no_operands`

Table Notes:

In addition to the normal operands that can be specified with this instruction, relocation operands can also be specified (see Section 2.6.4).

A number of the floating-point instructions in Table A-2 support qualifiers that control rounding and trapping modes. Table notes identify the qualifiers that can be used with a particular instruction. (The notes also identify the isntructions on which relocation operands can be specified.) Qualifiers are appended as suffixes to the particular instructions that support them, for example, the instruction cvtdg with the sc qualifier would be coded cvtdgsc. The qualifier suffixes consist of one or more characters, with each character identifying a particular rounding or trapping mode. Table A-3 defines the rounding or trapping modes associated with each character.

Table A-2: Floating-Point Instruction Set Summary

Instruction	Mnemonic	Operands
Load F_Floating Load G_Floating (Load D_Floating) Load S_Floating (Load Longword) Load T_Floating (Load Quadword)	ldf[Table Note 1] ldg[Table Note 1] lds[Table Note 1] ldt[Table Note 1]	`d_reg,address`
Store F_Floating Store G_Floating (Store D_Floating) Store S_Floating (Store Longword) Store T_Floating (Store Quadword)	stf[Table Note 1] stg[Table Note 1] sts[Table Note 1] stt[Table Note 1]	`s_reg,address`
Load Immediate F_Floating Load Immediate D_Floating Load Immediate G_Floating Load Immediate S_Floating Load Immediate T_Floating	ldif ldid ldig ldis ldit	`d_reg, val_expr`
Branch Equal to Zero Branch Not Equal to Zero Branch Less Than Zero Branch Less Than or Equal to Zero Branch Greater Than Zero Branch Greater Than or Equal to Zero	fbeq fbne fblt fble fbgt fbge	`s_reg, label` or `label`
Floating Clear	fclr	`d_reg`
Floating Move Floating Negate Floating Absolute Value Negate F_Floating Negate G_Floating Negate S_Floating Negate T_Floating	fmov fneg fabs negf[Table Note 2] negg[Table Note 2] negs[Table Note 3] negt[Table Note 3]	`s_reg, d_reg` or `d_reg/s_reg`
Copy Sign Copy Sign Negate Copy Sign and Exponent Move if Equal to Zero Move if Not Equal to Zero Move if Less Than Zero Move if Less Than or Equal to Zero Move if Greater Than Zero Move if Greater Than or Equal to Zero Add F_Floating Add G_Floating Add S_Floating Add T_Floating Compare G_Floating Equal Compare G_Floating Less Than Compare G_Floating Less Than or Equal Compare T_Floating Equal Compare T_Floating Less Than Compare T_Floating Less Than Compare T_Floating Unordered Compare T_Floating Less Than or Equal Divide F_Floating Divide G_Floating Divide S_Floating Divide T_Floating Multiply F_Floating Multiply G_Floating Multiply S_Floating Multiply T_Floating Subtract F_Floating Subtract G_Floating Subtract S_Floating Subtract T_Floating	cpys cpysn cpyse fcmoveq fcmovne fcmovlt fcmovle fcmovgt fcmovge addf[Table Note 4] addg[Table Note 4] adds[Table Note 5] addt[Table Note 5] cmpgeq[Table Note 2] cmpglt[Table Note 2] cmpgle[Table Note 2] cmpteq[Table Note 3] cmptlt[Table Note 3] cmptlt[Table Note 3] cmptun[Table Note 3] cmptle[Table Note 3] divf[Table Note 4] divg[Table Note 4] divs[Table Note 5] divt[Table Note 5] mulf[Table Note 4] mulg[Table Note 4] muls[Table Note 5] mult[Table Note 5] subf[Table Note 4] subg[Table Note 4] subs[Table Note 5] subt[Table Note 5]	`s_reg1, s_reg2, d_reg` or `d_reg/s_reg1, s_reg2`

Convert Quadword to Longword Convert Longword to Quadword Convert G_Floating to Quadword Convert T_Floating to Quadword Convert Quadword to F_Floating Convert Quadword to G_Floating Convert Quadword to S_Floating Convert Quadword to T_Floating Convert D_Floating to G_Floating Convert G_Floating to D_Floating Convert G_Floating to F_Floating Convert T_Floating to S_Floating Convert S_Floating to T_Floating	cvtql[Table Note 6] cvtlq cvtgq[Table Note 7] cvttq[Table Note 8] cvtqf[Table Note 9] cvtqg[Table Note 9] cvtqs[Table Note 10] cvtqt[Table Note 10] cvtdg[Table Note 4] cvtgd[Table Note 4] cvtgf[Table Note 4] cvtts[Table Note 5] cvtst[Table Note 2]	`s_reg, d_reg` or `d_reg/s_reg`
Move From FP Control Register	mf_fpcr	`d_reg`
Move To FP Control Register	mt_fpcr	`s_reg`
Floating No Operation	fnop	`no_operands`

Table notes:

In addition to the normal operands that can be specified with this instruction, relocation operands can also be specified (see Section 2.6.4).
s
su
c, u, uc, s, sc, su, suc
c, m, d, u, uc, um, ud, su, suc, sum, sud, sui, suic, suim, suid
sv, v
c, v, vc, s, sc, sv, svc
c, v, vc, sv, svc, svi, svic, d, vd, svd, svid
c
c, m, d, sui, suic, suim, suid

See the text immediately preceding Table A-2 for a description of the table notes.

Table A-3: Rounding and Trapping Modes

Suffix	Description
`(no suffix)`	Normal rounding
`c`	Chopped rounding
`d`	Dynamic rounding
`m`	Minus infinity rounding
`s`	Software completion
`u`	Underflow trap enabled
`v`	Integer overflow trap enabled
`i`	Inexact trap enabled

Operand Specifier	Description
`address`	A symbolic expression whose effective value is used as an address.
`b_reg`	Base register. A register containing a base address to which is added an offset (or displacement) value to produce an effective address.
`d_reg`	Destination register. A register that receives a value as a result of an operation.
`d_reg/s_reg`	One register that is used as both a destination register and a source register.
`label`	A label that identifies a location in a program.
`no_operands`	No operands are specified.
`offset`	An immediate value that is added to the contents of a base register to calculate an effective address.
`palcode`	A value that determines the operation performed by a PAL instruction.
`s_reg, s_reg1, s_reg2`	Source registers. Registers whose contents are to be used in an operation.
`val_expr`	An expression whose value is used as an absolute value.
`val_immed`	An immediate value that is to be used in an operation.
`jhint`	An address operand that provides a hint of where a `jmp` or `jsr` instruction will transfer control.
`rhint`	An immediate operand that provides software with a hint about how a `ret` or `jsr_coroutine` instruction is used.